how to do gate level simulation on modelsim?

[cherjier]

modelsim gate level simulation

hi,
i had done the behavioral simulation had pass but fail after implement on the FPGA. i would like to do the gate level simulation on modelsim but i could not find any tutorial or guide regarding it. can anyone suggest me a link or guide? please enlighten me..thank you.

 

[echo47]

gate level simulation modelsim

Try the ISE "Synthesis and Simulation Design Guide", chapter "Simulating Your Design", section "Simulation Points in HDL Design Flow". It describes various points during synthesis and routing where you can run a simulation. The only one of those intermediate steps that I've tried is the last one, "Timing Simulation Post-Place and Route".

It's been a long time since I've done that from ISE Project Navigator (I normally use batch files), but try the "Generate Post-Place & Route Simulation Model" under the "Place & Route" item in the Process tree.

 

[shahid Shafique]

gate level simulation using modelsim

Can i get the soft copy of the mentioned book

 

[Iouri]

fpga gate level simulation

www.xilinx.com

 

[echo47]

gate level simulation

That book is simply one of the manuals included with the Xilinx ISE software installation. They are also available here:
https://www.xilinx.com/support/sw_manuals/xilinx92/download/

 

[cherjier]

gate level simulation ise

thanks for all the reply.

i think i slightly get the idea of how to do it on xilinx ise or modelsim.

the ISE simulator seem like a only a lite version and it only able to simulate small design only.

the document can be found under the software manual which included once u install the xilinx tools.

i have another query regarding the glbl.v which define the GSR and GTS signal how define these signal on actual design implementation? since i need to define this 2 signal on my testbench. any tips?

 

[echo47]

gate level simulation fpga

If your FPGA logic needs to drive GSR or GTS, then search your ISE Libraries Guide for a special primitive such as STARTUP_SPARTAN3 (substitute your FPGA type name). However, most projects don't need to do this.

I've never explicitly used GSR or GTS in any of my projects. During simulation, I simply include glbl.v into the list of files being compiled so the testbench can properly initialize the various Xilinx library primitives that require them. If you launch ModelSim from ISE Project Navigator, I think it automatically includes glbl.v somehow. (I normally run ModelSim from a command-line script.)

I'm not familiar with ISE's simulator, sorry.

 

[cherjier]

gate level simulations

thanks for all the reply.
i successfully run the simulation on modelsim:
this is what i do:
in modelsim,just compile the simprims lib and the glbl.v together.
to start simulate,click the simulate button,then select the glbl and testbench then click ok. the simulation waveform will pop up. thanks for the help