how to do DFT with black box IP

[newcpu]

set_wrapper_element xg

Hi,
When I do dft, there are some black boxes IP such as dsp, cpu. If I just bypass them, there are Errors of clocks connected to these IP. What should I do? And when doing ATPG in TetraMax, there are also some scan chain Errors because of clocks related to these black boxes IP. How to solve them?

Best Regards,
newcpu

 

[AlexWan]

set_wrapper_element

Are there some test ports in your black-box IP?

 

[jcchan]

shadow_wrapper

The DSP IP core must have scan chain for DFT

 

[aravind]

u must do shadow logic for black box test.
u can shadow logic command in dc or rtl.
inside of bb u must put one flop assuming that this flop i s bb and complete the scan chain

 

[jackson_peng]

if the black box IP has test protocol, then read in it other than the IP module, in DFT scan-chain insertion.

Otherwise, the black box IP can't perform DFT on it. and you should add bypass logic on its output for scan insertion. and the IP vendor should also provide other way of testing rather than DFT.

 

[newcpu]

Thanks a lot.
The DSP was asked to test separately and scan ports of DSP were reserved. The DSP black box itself need not do DFT, but the top soc need dft. So I can bypass the DSP black box. But there are clocks inputed to the DSP black box and clocks outputed from it. If I directly connect the clocks inputed to the DSP black box and clocks outputed from it together, are there any problems of logic or timing? What should I do?

Best Regards,
newcpu

 

[Elias.xie]

That's ok, you can do it, but you should make sure this connection should only really exists when chip in scan test mode.

 

[HolySaint]

Are there some test ports in your black-box IP?

when it has ports, how can i connect in dftc?
thanks

 

[sunilbudumuru]

Hi Friend,

It is very simple.

If you are using XG mode of DFT Compiler,

You just add control and observe testpoints in the script around the BB cores as shown below.

set_testability_configuration -type observe -clock_signal [get_ports [list YOUR_TEST_CLOCK ]]
set_testability_configuration -type control -clock_signal [get_ports [list YOUR_TEST_CLOCK ]]

//Adding observe points
set_test_point_element -type observe [get_object_name [get_pins A/B/<DRIVER CELL OF BB1 inputs>/Y]] \
-clock_signal YOUR_TEST_CLOCK \
-power_saving enable


//Adding control points
set_test_point_element -type control_01 [get_object_name [get_pins A/B/BB1/Y]] \
-clock_signal YOUR_TEST_CLOCK

Where BB1 is your black box.

If you are using DB mode,
set_wrapper_element A/B/BB1 -type shadow
set_port_configuration -cell <BB1> -port CLK -wrapper_exclude

//besure to exclude key ports if necessary

set_def_configuration -shadow_wrapper -autofix

create_test_protocol
dft_drc
insert_dft
..
.

Hope this helps your problem.

Sunil Budumuru,
www.asic-dft.com