How to divide or generate clock from DCM in Spartan 3E500? (Verilog)

[aafaq]

can any one tell me about how i can devide or generate clock from DCM in the FPGA in verilog source

 

[kvingle]

Re: DCM in Sparton 3E500

refer this xilinx doc ....It is having the verilog as well as vhdl instantiation templates for the DCM
you can also use the 'Architecture wizard' present in the xilinx accessories.
refer the user guide for more details...

 

[echo47]

DCM in Sparton 3E500

Since you are using a Spartan-3E, also see the special DCM_SP primitive in your Spartan-3E Libraries Guide, in your ISE documentation.

Here's a Verilog example that generates 44100 Hz from 50 MHz using two DCM frequency synthesizers and a counter:
#738182