Feb 25, 2008 #1 A aafaq Newbie level 4 Joined Feb 25, 2008 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,309 can any one tell me about how i can devide or generate clock from DCM in the FPGA in verilog source
Feb 25, 2008 #2 K kvingle Full Member level 5 Joined Nov 5, 2007 Messages 244 Helped 33 Reputation 66 Reaction score 12 Trophy points 1,298 Location India. Activity points 2,574 Re: DCM in Sparton 3E500 refer this xilinx doc ....It is having the verilog as well as vhdl instantiation templates for the DCM you can also use the 'Architecture wizard' present in the xilinx accessories. refer the user guide for more details...
Re: DCM in Sparton 3E500 refer this xilinx doc ....It is having the verilog as well as vhdl instantiation templates for the DCM you can also use the 'Architecture wizard' present in the xilinx accessories. refer the user guide for more details...
Feb 25, 2008 #3 E echo47 Advanced Member level 6 Joined Apr 7, 2002 Messages 3,933 Helped 638 Reputation 1,274 Reaction score 90 Trophy points 1,328 Location USA Activity points 33,176 DCM in Sparton 3E500 Since you are using a Spartan-3E, also see the special DCM_SP primitive in your Spartan-3E Libraries Guide, in your ISE documentation. Here's a Verilog example that generates 44100 Hz from 50 MHz using two DCM frequency synthesizers and a counter: #738182
DCM in Sparton 3E500 Since you are using a Spartan-3E, also see the special DCM_SP primitive in your Spartan-3E Libraries Guide, in your ISE documentation. Here's a Verilog example that generates 44100 Hz from 50 MHz using two DCM frequency synthesizers and a counter: #738182