sakshi gupta
Full Member level 1

good case
module testve_vlg155(out1, in , clock , reset );
input clock , reset, in;
output reg [2:0] out1;
reg [2:0] out2;
reg [1:0] i ;
always @ ( posedge clock or negedge reset )
begin
if (reset == 0 )
begin
out1<=0;
out2 = 0; // good -- out2 is TEMP variable
end
else
begin
for ( i=0 ; i<3 ; i=i+1 )
out2 = out2 + i;
out1<= out2;
end
end
After synthesis , both out1 & out2 will be inferred as flop . How we can make tool understand that out2 is temporary variable & out1 is Flop ?
module testve_vlg155(out1, in , clock , reset );
input clock , reset, in;
output reg [2:0] out1;
reg [2:0] out2;
reg [1:0] i ;
always @ ( posedge clock or negedge reset )
begin
if (reset == 0 )
begin
out1<=0;
out2 = 0; // good -- out2 is TEMP variable
end
else
begin
for ( i=0 ; i<3 ; i=i+1 )
out2 = out2 + i;
out1<= out2;
end
end
After synthesis , both out1 & out2 will be inferred as flop . How we can make tool understand that out2 is temporary variable & out1 is Flop ?