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How to distinguish between Flop & temp variable ?

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sakshi gupta

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good case
module testve_vlg155(out1, in , clock , reset );
input clock , reset, in;
output reg [2:0] out1;
reg [2:0] out2;
reg [1:0] i ;

always @ ( posedge clock or negedge reset )
begin
if (reset == 0 )
begin
out1<=0;
out2 = 0; // good -- out2 is TEMP variable
end
else
begin
for ( i=0 ; i<3 ; i=i+1 )
out2 = out2 + i;
out1<= out2;
end
end


After synthesis , both out1 & out2 will be inferred as flop . How we can make tool understand that out2 is temporary variable & out1 is Flop ?
 

I don't have time to do tests on this, but I think out2 is flops because you use it to remember the value from the previous clock edge. Try to eliminate that by adding the following line just before the "for" loop:

out2 = out1;

This means that out1 is used to remember the previous value instead of out2. Out2 will start from scratch every clock cycle and will not need flops.
 

out2 is flop because the values are changed inside an "always @(posedge clk)" block. This means the out2 value is updated at each clock cycle which is done with flops.

If you want logic instead of flops you must perform the assigment like this:

always (i)
begin
out <= out + 1;
end

Problem is, since out depends on the previous value, the result will be a latch instead of a flip-flop. Latches on circuits is always a bad idea.
 

You could move out the synchron process the combinational logic in a asynchronous process
 

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