How to display the output of floating point Verilog program on Spartan 6 FPGA kit????

[vishal011990]

Hello Sir/Madam,
I have Spartan6 FPGA SP605 Evaluation kit. Using IP core generator, I wrote the program of floating point addition/subtraction program and I downloaded into the kit. But I have problem regarding to display result. So, plz suggest me a solution for that.
One more doubt, How can we give the input value to HDL program?????

 

[kingslayer]

Dear,

you basically have two ways to input a value to an IP block: either from hardware or from software. In the first case you have to modify the VHDL design of your top-level block that instantiates the component, and apply the desired signals to the inputs. However, if you are talking about IP cores, they come with a bus interface, so using EDK you can attach the generated core as slave to the peripheral bus, map the core to memory and write to the inputs as they were registers (indeed, they are) from software running on the on-chip processor.

Cheers