module Display_7Seg (a_out, b_out, c_out, d_out,e_out,f_out,g_out,db_out, Clk_in);
output a_out, b_out, c_out, d_out,e_out,f_out,g_out,db_out;
input Clk_in;
reg ctr_8bits;
always @(Clk_in)
case (ctr_8bits)
8'h00 :
-- draw Zero
a_out = 0, b_out = 0, c_out = 0, d_out = 0,
e_out = 0, f_out = 0, g_out = 1 ,db_out = 1;
8'b01 :
-- Draw 1
a_out = 1, b_out = 0, c_out = 0, d_out = 1,
e_out = 1, f_out = 1, g_out = 1 ,db_out = 1;
2'b10 :
-- Draw 2
a_out = 0, b_out = 0, c_out = 1, d_out = 0,
e_out = 0, f_out = 1, g_out = 0 ,db_out = 1;
endcase
endmodule