How to disable VHDL assertions from System verilog class?

[er.akhilkumar]

Hello All,

I am facing problem in disabling an assertion written in RTL by using $assert_off or $assert_kill in System verilog class.

the example given on internet is as following:

$assert_off(1,testbench_top.assertion_name);

The above code is valid for the assertions written at testbench top. If I want to disable the assertion written at RTL level. How can I disable them?

I have written the code as following for disabling the RTL assertions but it reports ncsim error:

$assert_off(1,tb_top.design_top:assertion_name);

I have also tried putting the heirarchy as string but failed.

Have you got any solution? I am using OVM based system verilog testbench and RTL written in VHDL.

Thanx.

 

[er.akhilkumar]

Please come with a solution...