How to determine the resistance value in flash ADC design?

[Friendcheng]

hello,everyone
Iam designing a flash adc now.
To generate the reference voltages, a resistive reference ladder has to be used, and my problem is i don't know how to determin the value of the resistence.
Can anyone tell me how to determin the value of the resistence?
can anyone give me the method in detail or the paper which explain it in detail.
Best regards.

 

[erikl]

flash adc

Lower limit: power consumption
Upper limit: 1. output resistance ≪ input resistance
2. sample or conversion time > RC * n * ln2

The order of magnitude of "≪" is 2^n , n being the resolution of the converter, i.e. e.g. a factor of 1024 ≈ 1000 for a 10-bit converter. RC < 1/7 * conv_time, in this case.

Plan your resistor chain values to be as high as possible, respecting the upper limit criteria.

 

[Friendcheng]

flash adc design

Thank you for your answer.

Can you explain the R and C in the following formaluation more clearly.

"sample or conversion time > RC * n * ln2"

and the following are my question of the above formulation

1.how does the formulation being obtained, can you recommend a paper which explain it in detail

2.does the R mean the whole resistence of the resistence chain?

3.does the C mean the whole capacitance of the preamplifiers,and it is equal to 2*Cgs*m, m is the number of the preamplifiers which connect to the resistence chain?

 

[kickbeer]

adc designs

hi friendcheng,

My dissertation is also to design a flash A/D-Converter. I will start this project at the end of March. HOpefully we can share our progress about this topic if you want and exchanging ideas on this if you want. Thanks

 

[erikl]

flash adc designs

Thank you for your answer.
Can you explain the R and C in the following formaluation more clearly.

R is the equivalent output (source) resistance of the resistor chain at that point where you connect this tap (eventually via a switch) to your measurement circuit (e.g. amplifier or comparator). C is the total equivalent capacitance at this very same point.

"sample or conversion time > RC * n * ln2"
and the following are my question of the above formulation

1.how does the formulation being obtained, can you recommend a paper which explain it in detail

This is such basic, that you just need your standard textbook on electricity ;-)
The inequation results from the standard formula of loading a C via an R :
V = V0 (1 - exp(-t/RC)) (s. your standard textbook on electrics)
... and the requirement, that the difference between the voltage level to be measured and the voltage level attained on C (via R) be less than the required resolution :
V0 - V = V0*exp(-t/RC)
V0/(2^n) < V0*exp(-t/RC)
-n*ln2 < -t/RC
t > RC * n * ln2

2.does the R mean the whole resistence of the resistence chain?

No, the equivalent source resistance at the tap, for each tap point, s. above!

3.does the C mean the whole capacitance of the preamplifiers,and it is equal to 2*Cgs*m, m is the number of the preamplifiers which connect to the resistence chain?

No, the equivalent capacitance at the tap (m=1), again for each tap point, s. above!

This means, you must respect the above inequation at every tap point of the resistor chain to the connected circuit. If the capacitance is (nearly) equal at every tap, the highest source resistance of the chain is in the (arithmetic) middle of the chain. This tap point must respect the above inequation.

HTH! erikl

 

[Friendcheng]

flash adc converter

I am very glad to exchange ideas with you.

hi friendcheng,

My dissertation is also to design a flash A/D-Converter. I will start this project at the end of March. HOpefully we can share our progress about this topic if you want and exchanging ideas on this if you want. Thanks

 

[safwatonline]

working of flash adc

don't forget about mismatch when going for smaller R

 

[kickbeer]

architecture of flash adc

hello friendcheng,

are you doing A/D converter with flash or folding architecture?

 

[Friendcheng]

how to design a flash adc

yes

hello friendcheng,

are you doing A/D converter with flash or folding architecture?

 

[kickbeer]

design of a flash adc

hello friendcheng,

flash or folding?

 

[Friendcheng]

design flash adc

hi, kickbeer

sorry for vague reply.

the architecture of the ADC i am designning now is the flash architecture.

 

[kickbeer]

folding and interpolation flash adc

hello friendcheng,

it's ok.Which type of comparator are using actually?

 

[chinacore]

power consumption in flash adc

hello friendcheng,

are you doing A/D converter with flash or folding architecture?

I am going to design a folding and interpolating adc.I am glad to exchange idea together.

 

[kickbeer]

adc design aspects

hi, kickbeer

sorry for vague reply.

the architecture of the ADC i am designning now is the flash architecture.

Hi friendcheng,

How's your progress with flash adc?

 

[Friendcheng]

10-bit flash adc

hello friendcheng,

are you doing A/D converter with flash or folding architecture?

I am going to design a folding and interpolating adc.I am glad to exchange idea together.

I am glad to exchange idea with you too
can we communicate by email?
my email is :lianlianhonghong@163.com

Added after 3 minutes:

hi, kickbeer

sorry for vague reply.

the architecture of the ADC i am designning now is the flash architecture.

Hi friendcheng,

How's your progress with flash adc?

I am glad to exchange idea with you too
can we communicate by email?
my email is :lianlianhonghong@163.com

 

[manish_tu]

formaluation

how to design poly metal capacitor layout