How to Determine the Gate Bias for PA?

[hunas2127]

I have selected the transistor size using the PDK guide.
I understand that the PA class is determined by the gate bias, and I am designing a Class A GaN PA.
I would like to know what an appropriate gate voltage value would be and how to determine it.


For example, should I initially select a random gate voltage, then perform load & source pull measurements to check the transistor's performance (Pout, PAE, Gain), and iteratively adjust the gate voltage until the desired specifications are met?

 

[D.A.(Tony)Stewart]

For Class A, aim for Idq ≈ 0.5 × Imax.
Initial Guess: Pick a Vgs slightly above Vth (e.g., Vth + 0.5 V for e-mode) (-0.5 for d-mode as in your case) as a starting point.
For Vdd use <90% Vds max for initial margin safety.
Check SOA and thermal curves or estimate heatsink rise from Rjc*Rth*P and thermal time constant.
Record Idq and Vds and adjust Vgs with a short pulse.

Do you have a tuner like a Maury Microwave system or equiv?
Calibrate the tuners to account for fixture losses to better than your error tolerance.
Semi-rigid coax is better with SMA.

PTC effects will increase the slope of your curves.

 

[dick_freebird]

You have a load and a supply, probably want
output positioned at center. Could do this by
fed-back voltage or current (my only forays into
amplifier bias control, used a drain sense resistor
to servo gate voltage (as this was radar panels,
the TX and RX were switched - no circulator -
and bias had to "snap in" pretty quickly.

Vg is a bid deal, noise-wise. Everything in your
MMIC is sitting there common-source-amplifying
anything that comes in on it.