Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to determine settling time of op-amp

Status
Not open for further replies.

thanhtri_pc

Junior Member level 2
Joined
Apr 18, 2010
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Vietnam
Activity points
1,458
Hi all,
I just draw a schematic to determine the settling time of Op-amp. I got the graph as the attachment.

I see that we must choos a poit B firstly and compare to poit A. But I don't know how to choose the point B? What condition should I base on to determine point B?
 

Settling time is usually defined to a percentage of final value. So, it might be to 0.1%. If you are simulating a particular opamp then it will give the conditions for the settling time measurement.

Keith
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top