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how to desin "start/pause button" in verilog

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thuyet

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verilog button

dear

Someone can help me how to design as a pause button. It means that when we first active it :=> it is START and next we press again :=> it is PAUSE .and continue

someone help me ideas please

Thank you very much:D
 

ls000rhb

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verilog pause

you maybe set 1 bit in register as start/pause_n signal, when you write 1 to this register, it starts,while wirte 0, it pause.

BR.
ls000rhb
 

avimit

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verilog pause

If the start/pause button is operated by a 'human' the dont forget to use 'key debounce' . Well when a human presses a button, it generates a noisy wave before setteling to a logic value. You will have to filter out this 'noise' or nothing would work as expected. Its very simple to do, just look for it in google.
Kr,
Avi
https://www.vlsiip.com
 

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verilog button

how to desin "start/pause button" in verilog ?

If I had understood your question I thing you should use a Finite State Machine.
Electrically speeking avimit gave you a solution if the button will be mechanically activated.
 

jason99pan

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verilog long pressed button

I agree with master_picengineer

You can use FSM to design these functions. if pause is pressed, the state can remain. The state will go on until the start is pressed.

You can try it, good luck!

B.R.
 

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