HOW TO DESIGN UART IN FPGA

[fan2005]

i know nothing , how can i design UART in FPGA, using HDL.thanks

 

[Engr.Kamran Hameed]

UART Scoreboard

1 class uart_sb;
2 mailbox tx = new();
3 mailbox rx = new();
4
5 task txAdd(bit [7:0] data);
6 begin
7 tx.put(data);
8 $write("%dns : txAdd : Added data %x\n",$time, data);
9 end
10 endtask
11
12 task rxAdd(bit [7:0] data);
13 begin
14 rx.put(data);
15 $write("%dns : rxAdd : Added data %x\n",$time, data);
16 end
17 endtask
18
19 task txCompare(bit [7:0] data);
20 begin
21 bit [7:0] org_data;
22 tx.get(org_data);
23 if (data ! = org_data) begin
24 $write("%dns : txCompare : Error : Expected data %x, Got %x\n",
25 $time, org_data, data);
26 end else begin
27 $write("%dns : txCompare : Match : Expected data %x, Got %x\n",
28 $time, org_data, data);
29 end
30 end
31 endtask
32
33 task rxCompare(bit [7:0] data);
34 begin
35 bit [7:0] org_data;
36 rx.get(org_data);
37 if (data ! = org_data) begin
38 $write("%dns : rxCompare : Error : Expected data %x, Got %x\n",
39 $time, org_data, data);
40 end else begin
41 $write("%dns : rxCompare : Match : Expected data %x, Got %x\n",
42 $time, org_data, data);
43 end
44 end
45 endtask
46 endclass







UART Transcation Generator



1 class uart_txgen;
2 uart_sb sb;
3 virtual uart_ports ports;
4 bit tx_done;
5 bit rx_done;
6
7 // Connects the transmitter output to recevier input
8 bit loopback;
9 // Number of frames to send to transmitter
10 integer no_tx_cmds;
11 // Number of frames to send to receiver
12 integer no_rx_cmds;
13 // Delay the reading of data from receiver
14 bit rx_over_flow;
15 // Send frame to transmitter before it has sent out last frame
16 bit tx_over_flow;
17 // Insert framming error (stop bit) in frame sent to receiver
18 bit rx_frame_err;
19
20 function new (virtual uart_ports ports);
21 begin
22 this.ports = ports;
23 sb = new();
24 tx_done = 0;
25 rx_done = 0;
26 no_tx_cmds = 5;
27 no_rx_cmds = 5;
28 rx_over_flow = 0;
29 rx_frame_err = 0;
30 ports.rx_tb_in = 1;
31 ports.uld_rx_data = 0;
32 end
33 endfunction
34
35 // Main method, which starts rest of methods
36 task goTxgen();
37 begin
38 tx_done = 0;
39 rx_done = 0;
40 assertReset();
41 fork
42 txDriver();
43 rxDriver();
44 txMonitor();
45 rxMonitor();
46 join_none
47 end
48 endtask
49 // This method asserts method
50 task assertReset();
51 begin
52 @ (posedge ports.rxclk);
53 ports.reset = 1;
54 $write("%dns : Asserting reset to Uart\n",$time);
55 repeat (5) @ (posedge ports.rxclk);
56 ports.reset = 0;
57 end
58 endtask
59
60 task txDriver();
61 begin
62 integer i = 0;
63 integer tx_timeout = 0;
64 bit [7:0] tx_data = 0;
65 ports.tx_enable = 1;
66 for (i = 0; i < no_tx_cmds; i ++) begin
67 tx_data = $random();
68 sb.txAdd(tx_data);
69 if (loopback == 1) begin
70 sb.rxAdd(tx_data);
71 end
72 // Check if uart is ready to accept data for transmission
73 while (ports.tx_empty == 0) begin
74 @ (posedge ports.txclk);
75 tx_timeout ++ ;
76 if (tx_timeout > 10) begin
77 $write("%dns : txDriver : Warning : tx_empty is 0 for more then 10 clocks\n",
78 $time);
79 end
80 end
81 tx_timeout = 0;
82 // Drive the data in UART for transmitting
83 @ (posedge ports.txclk);
84 ports.ld_tx_data = 1;
85 ports.tx_data = tx_data;
86 $write("%dns : txDriver : Transmitting data %x\n",$time, tx_data);
87 @ (posedge ports.txclk);
88 ports.ld_tx_data = 0;
89 ports.tx_data = 0;
90 while (ports.tx_empty == 1) begin
91 @ (posedge ports.txclk);
92 tx_timeout ++ ;
93 if (tx_timeout > 10) begin
94 $write("%dns : txDriver : Warning : tx_empty is 1 for more then 10 clocks\n",
95 $time);
96 end
97 end
98 tx_timeout = 0;
99 end
100 tx_done = 1;
101 end
102 endtask
103
104 task rxDriver();
105 begin
106 bit [7:0] rx_data = 0;
107 integer i,j = 0;
108 ports.rx_enable = 1;
109 if (loopback == 1) begin
110 ports.loopback = 1;
111 end else begin
112 ports.loopback = 0;
113 for (i = 0; i < no_rx_cmds; i++) begin
114 rx_data = $random();
115 sb.rxAdd(rx_data);
116 $write("%dns : rxDriver : Transmitting data %x\n",$time, rx_data);
117 @ (posedge ports.txclk);
118 ports.rx_in = 0;
119 for (j = 0; j < 8; j ++) begin
120 @ (posedge ports.txclk);
121 ports.rx_in = rx_data[j];
122 end
123 @ (posedge ports.txclk);
124 ports.rx_in = 1;
125 @ (posedge ports.txclk);
126 end
127 end
128 rx_done = 1;
129 end
130 endtask
131
132 task txMonitor();
133 begin
134 bit [7:0] tx_data = 0;
135 integer i = 0;
136 while (1) begin
137 @ (posedge ports.txclk);
138 if (ports.tx_out == 0) begin
139 $write("%dns : txMonitor : Found start of frame\n",$time);
140 for (i = 0; i < 8; i ++) begin
141 @ (posedge ports.txclk);
142 tx_data = ports.tx_out;
143 end
144 @ (posedge ports.txclk);
145 if (ports.tx_out == 0) begin
146 $write("%dns : txMonitor Error : Framing error detecting\n",$time);
147 sb.txCompare(8'b0);
148 end else begin
149 $write("%dns : txMonitor : Sampled data %x\n",$time, tx_data);
150 sb.txCompare(tx_data);
151 end
152 end
153 end
154 end
155 endtask
156
157 task rxMonitor() ;
158 begin
159 bit [7:0] rx_data = 0;
160 while (1) begin
161 @ (posedge ports.txclk);
162 if (ports.rx_empty == 0) begin
163 ports.uld_rx_data = 1;
164 @ (posedge ports.txclk);
165 rx_data = ports.rx_data;
166 ports.uld_rx_data = 0;
167 $write("%dns : rxMonitor : Sampled data %x\n",$time, rx_data);
168 sb.rxCompare(rx_data);
169 @ (posedge ports.txclk);
170 end
171 end
172 end
173 endtask
174
175 function bit isDone();
176 begin
177 if (tx_done == 1 && rx_done == 1) begin
178 isDone = 1;
179 end else begin
180 isDone = 0;
181 end
182 end
183 endfunction
184 endclass












Ports File


1 `ifndef UART_PORTS_SV
2 `define UART_PORTS_Sv
3
4 interface uart_ports (
5 output logic reset ,
6 input wire txclk ,
7 output logic ld_tx_data ,
8 output logic [7:0] tx_data ,
9 output logic tx_enable ,
10 output logic tx_out ,
11 input wire tx_empty ,
12 input wire rxclk ,
13 output logic uld_rx_data ,
14 input wire [7:0] rx_data ,
15 output logic rx_enable ,
16 output logic rx_in ,
17 input wire rx_empty ,
18 output logic loopback ,
19 output logic rx_tb_in
20 );
21 endinterface
22
23 `endif

 

[calm]

you can see abi88's post on this bullet.

 

[thuyet]

dear
log on digilent website,they have good example uart. I used it and found very good.download for your reference.It is easy to used

 

[salma ali bakr]

if you have FPGA advantage
then it's implemented already there

 

[keerthiraj]

give me ur mail id... i hav one code .... i'l send it to u.. may be it vil help u..