Dec 3, 2007 #1 rajakash Member level 2 Joined Nov 9, 2006 Messages 53 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,608 hi friends.. how do design timer and PLL using VHDL.. if anyone have sample code sent it thanks..
Dec 3, 2007 #2 I Iouri Advanced Member level 2 Joined Aug 17, 2005 Messages 678 Helped 87 Reputation 174 Reaction score 8 Trophy points 1,298 Activity points 4,814 timer and pll Pll is FPGA internal resource Timer is VHDL/Verilog code what you need to write