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How to design the switch in PipeLine ADC?

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wjxcom

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Hi all: I am designing a 10bits 50MHz PipelineADC, the common voltage is 1.65V, the possive reference voltage is 1.9V and the negative voltage is 1.4V.
the wave of 1024 points fft is shown below:
fft.JPG

But there have some wrong with this circuit:
1, In the SampHold circuit, the output of SampHold circuit SHN and SHP. From the simulation result, I find that the common voltage in sample phase and in amplify phase is different. the simulation result is shown below:
shn_shp_edaboard.JPG

2. In the 8th stage, the output of 8th stage is VON8 and VOP8. From the simulation result, I find that the common voltage in sample phase and in amplify phase is different. the simulation result is shown below:
von8_vop8_edaboard.JPG

3. The result of VON8-VOP8 is strange! from the wave of VON8-VOP8, I found that at the beginning of the simulation, the valut of VON8-VOP8 is 170mV, then the valut of VON8-VOP8 becomes smaller step by step, and at the end of the simulation, the value of VON8-VOP8 is about 127mV. the simulation rusult is shown below:
vo8_1_edaboard.JPGvo8_2_edaboard.JPG**broken link removed****broken link removed**

I think the size of switch is not designed carefully which causes these problems. But I do not know how to design the switch? Help me please, thax!!

My be I need to upload my circuit, then somebody can simulate it.
 

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  • eetop.cn_PIPELINE_ADC_10BITS_50MHz_20130624.tar.gz
    861.9 KB · Views: 54
  • eetop.cn_smic18mm2008.zip
    6.5 MB · Views: 56

Nobody can help me, maybe my question is so difficult, or so easy?
 

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