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how to design otp array layout

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hi all,

i was told to design a 512 bit otp(one time programmable)layout .
i know the array that has 64 row, 8 line and per cell has two mos, one transistor,another capacitor.
You know totoal 1024 mos in the array, i don't konw how to explort efficiently the many many transistor in the layout

Please someone tell me.



with regards
founder
 

Dear erikl,

Thanks your suggestion, only that 1.8v transistor was used to breakdown as if a capactor in an OTP.
Again thank you ! & the question has been answered.
And i have a new question: Extract capacitance

1, i finished the DRC&LVS of OTP array layout
2, My boss asked me to extract its capacitance and campare it with my calculation

Question: How to calculate the capacitance of a cell OTP array?

Due to the intrinsic capacitances of MOS transistor are concerned with its apply voltage,
only under the layout known, i don't konw how to calculate capacitance and compare it with extract capacitance

Please help
Thanks once again

Best regards
Founder
 

For each node of interest, add all its extracted capacitances!
 

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