How to design IC test pad

[wangkes9]

I have brought a wirebond machine recently. So I want to set some pad for test
in my newly-designed chip, this chip is only for research.

So can I ignore the ESD part of the IO ? only metal lay and pad layer. Of course, when I do test , I will do my best to prevent the static electronic and limit the supply voltage in a permitted range.

I want to know whether the chip will be damaged easily if I design and test like this without ESD and protection IO circuit? Thanks.

 

[zhongdg]

I think you should to have ESD protection for the static electronic caused by test equipment. It can only waste a little area. Why not add ESD protecion?

 

[wangkes9]

I have used some standard analog IO given by faundry.

The pad area is 75*75um^2, and the other part including ESD is 75*300um^2.
So I want to take out it.

Can you introduce me a simple ESD architecture.

 

[prcken]

ESD is not protable for different process
i think you should include ESD protection device for your test chip, although you will not do ESD testing.
but you can find if there is ESD induced effect in your core ckt or not

 

[walker5678]

Maybe just place two diode as ESD protection. The area of the diode should be large enough.

 

[forkschgrad]

there are different ESD protection set-up. different clampers.

 

[jecyhale]

You'd better use the ESD, but use a small diode ESD.
I is easy to design.

 

[randell_xtian]

always engaged the ESD as a part of precaution in designing an IC. it serves a vital role in protecting even in testing the IC.

 

[oxplorer]

it's ok without esd but be careful

 

[randell_xtian]

hu? without the ESD, the IC will have a static voltage if you handle it with bare hand. 25kV would cause a serious damage to your IC. think of it.!

randell_xtian

 

[ESDSolutions]

Can you provide further details about your query?

- Do you design in 130nm technology or smaller node? Starting from 130nm ESD protection concepts are getting more complex and core elements are extremely sensitive to ESD.

- What kind of devices are connected to the pad? If these are core devices without ESD guidelines applied (see foundry Design rule manual) then you should expect a low yield.

- Are you going to package the samples before making measurements. Most assembly houses will not guarantee yield on the bonding if no on-chip ESD is provided

- Are you worried for the area of for the capacitance? Does you IO need >500MHz operation? Then you need to worry about parasitic capacitance.

Get in touch with the foundry or its preferred ESD partner when you have answered positive on 3 of the 4 questions. In other cases just use the pad provided. Make sure you include a ESD pad for the Vdd/Vss pads as this is necassary to protect the core of your IC.