Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A DPLL is consist of 3 parts typicallyD,K counter and the I/D divider.
PDhase detector, is used to detect the phase difference between the incoming signal(Ref Frequency) and the output of the DPLL(fedback from the output); PD will output the up or dn signals to indicate the phase difference.
K counter functions as a loop filter,it will output a carry or borrow pulse when the counter equal to the predefined K, and the counter is gotten via sampling the up/dn signals output from PD.
I/D divider is a controlled divider.It will output a central frequency by dividing a particular number. However, the division ration will be controlled by the carry/borrow pulse from the K Counter.
the output of the I/D divider will be feed back to the PD.
I have just finished demo,the most difficult thing is programmable frequence generation,The PD can be finded at @ltera,it is good.but i have not find a good way to know whether the verifying freqence is the same of the reference