How to design DPLL? Request for resources

[cslover]

DPLL

How to design DPLL. if you have doc about DPLL, please send it to me .
Thanks advance.

 

[papyaki]

Hi

You can look at :

h**p://w*w.actel.com/documents/s04_18.pdf

 

[RTL2GDSII]

I am very interested in this topic too.
Any more in-depth info ?

 

[papyaki]

Hi

There is also this ap note from Texas Inst.

h**p://www-s.ti.com/sc/psheets/sdla005b/sdla005b.pdf

 

[arena_yang]

A DPLL is consist of 3 parts typicallyD,K counter and the I/D divider.
PDhase detector, is used to detect the phase difference between the incoming signal(Ref Frequency) and the output of the DPLL(fedback from the output); PD will output the up or dn signals to indicate the phase difference.

K counter functions as a loop filter,it will output a carry or borrow pulse when the counter equal to the predefined K, and the counter is gotten via sampling the up/dn signals output from PD.

I/D divider is a controlled divider.It will output a central frequency by dividing a particular number. However, the division ration will be controlled by the carry/borrow pulse from the K Counter.

the output of the I/D divider will be feed back to the PD.

Then a phase locked LOOP is constructed!!

 

[homeadd]

I have just finished demo,the most difficult thing is programmable frequence generation,The PD can be finded at @ltera,it is good.but i have not find a good way to know whether the verifying freqence is the same of the reference