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How to design digital ajustable FIR filter?

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Raidum226

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How to design a digital FIR filter with cutoff frequency range from 4MHz to 6MHz? And we don't have any multiplier, we just have some adders.

If we just need a FIR filter with cutoff frequency = 4MHz, and sampling frequency = 20MHz. We can use Matlab to generate the FIR filter coefficient. Last, we can use adders to implement this filter.(or multiply a number by a const).

But If we need a FIR filter with cutoff frequency range from 4MHz to 6MHz, how to inplment it without using multipliers.(just use const. multipliers)

Any possobility?
 

brmadhukar

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Hi,
1. The easiest solution (however expensive) is to design many filters and choose one of them depending on the bandwidth.

1a. If you are using an FPGA, there is no wastage of resources so you may load 6MHz filter instead of 4MHz filter

2. Try to find a cascaded filter structure and you may use only the required number of stages.

hope this helps,
brmadhukar
 

Raidum226

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Where can I get the information of cascade FIR filter?
Is a cascade FIR filter cost very much?

BR,
 

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