how to design cmos high speed analog comp

[andy2000a]

design cmos

vcc=3.3v ~ 12v , and compare volt=500mv , delaytime < 5ns
and input is pulse signal < 10ns , no clock signal for latch

how to design this high speed comparate ?
which topology be suit ? 2_stage or foldcascode ?
I think 2 stage is small area but speed is slow ..


thank you

 

[andy2000a]

by the way , if we use 2 stage OPA-> comparator
can we meet delay time < 20ns ..

I think 2 stage OPA is easy design than others..

 

[gevy]

I think, that is necessary to use the following cascades: folded cascode, current comparator and digital inverters series connected.

 

[konqueror]

in 2 stage comparator speed is less so
use a regenerative(hysteresis) comparator.
it can give u very fast speeds.u can refer to
"cmos analog circuit design" by
allen & hollberg for designing details of
comparators with hysteresis

 

[CDRCDR]

I would recommend a preamplifier and then followed by latch circuit

 

[yeewong_su]

2 stage simple opamp and inverter driver output.
latch circuit will add it's difficult

 

[Colbhaidh]

Vcc = 3V3 -> 12V !! Are you sure ????
This is impossible in CMOS !!

 

[qslazio]

simple preamp and 2 inverter will meet your requirement

 

[james_su]

Don't use the latch ckt if you not use the clock signal

 

[icsrc]

i've never seen 12V supply in CMOS process

 

[electronrancher]

Please guys - the post is about comparators, not whether you have personally seen a 12v gate. I have a process with 5v, 16v, and 30v gates that I use quite often. I suggest you guys keep looking.

back to Andy's question....

The trick will be keeping the (Internal) voltage swings small in order to be fast. Current comparator style is OK, but clamp the nodes so they can't swing Vdd-GND else it will be very slow.

I am thinking of a cascade of 3 low-gain (10 or less) diff amps (outputting to resistors), then a low-voltage to high-voltage translator. The final output would be an inverter. The trick is you need to drive that inverter's gate from 0-VDD, but the output of the last diff stage is probably 0-1v. You could use two NMOS to flip a level-shift, but I don't know if it would be fast enough.

You could probably get through the diff amps in 2-3ns, but driving that output inverter may be slower than you can tolerate.

The Li book (CMOS ckt dsn, simulation, and layout) has a 10ns comparator that may work for you if you can't get a 2ns level shift.