How to design a nice PLL?

[stephenpan]

pll design report

hi
I want to design a PLL.
I meet some problems:

1.how to make PFD to "ZERO DEAD-ZONE"
2.how to measue the jitter? soft or info..

if someone has the experience,plz help me..

n...ASIC Design Methodologies & Tools
so good Forum!!

THANX!!

 

[roli]

What do you mean by PFD (Phase-Frequency Detector ...???) ?

Anyways, there are many types of PD (Phase Detectors: 2-state, 3-state, etc. And each type works a little bit dirrerent for the type of data fed into the PLL: RZ, NRZ , NRZ Square, etc.

I've attached (scanned just now for you - from one of my BEST books - you should buy it : "Phase-Locked Loop Circuit Design" by Dan H. Wolaver - Prentice Hall, ISBN 0-13-662743-9), 3 types of PDs (there are more...)
1. XOR based,
2. 2-state for NRZ data,
3. 2-state for Square NRZ data.

The 2 later are suitable for Clock Recovery.
To use them as Frequency, one must change mainly the Loop-Filter (a narrower Wn...)

A quality measure of jitter can be measured at the output of you filter.

Hope this helps...
roli

Uploaded file: **broken link removed**

 

[bird123]

Does anyone have pdf version of "Phase-Locked Loop Circuit Design" book ?

 

[roli]

This is a 300 pages book. No way I can scan it manually. Is there an automatic way ?

 

[coolsniper]

Syst*mVu is a good simulation tool on PC.
Now Ver5.1 is available.

 

[weichi1211]

i have an introduction for u


Uploaded file: **broken link removed**

 

[rfsystem]

The issue 1. is because of the following problem:

If the reference phase and the divided VCO phase arrive at the same time the PFD set both UP and DOWN outputs to high. But after a small internal propagation delay time these are reset. If the charge pump current source has rise and fall times of the currents it could happen that the UP or DOWN pulse is reset before the current could rise to its final value. In effect the charge delivered over one period is not proportional to the UP or DOWN pulse time. If you model the rise/fall behaviour with linear edges the charge behaviour is a square function over the phase difference if the pulse width is less than the complete edge rise/fall. So in practice there is no dead zone but a zone with less gain approaching zero at zero phased difference. You could avoid that simply by introducing in the reset path of the PFD a delay which should be higher than the current source settling time in the charge pump.

 

[az25]

On 2002-02-21 07:05, bird123 wrote:
Does anyone have pdf version of "Phase-Locked Loop Circuit Design" book ?

I think National has it and software too. You can find at **broken link removed** (Search for it).
az25

 

[prisnow]

If anyone upload the Electronic Version of
"Digital PLL design" book,I will be thankful
very much.

 

[dacadc]

I have book in Russian, "Digital PLL systems design". Interesting?

 

[yellowtooth]

dacadc,
R U Russian ?
Or U R kidding ?

 

[stephenpan]

thanx for roli's info

as rfsystem said,I see the same view on IEEE
papers.It did improve the linearity of the PLL system.

But how to measure the jitter of the pll by simulation.& how small of the jitter is,we can say the pll is goo design?

thanx a lot~

 

[TheMick]

Analog Device have a nice free tool at present on their web site for doing loop stability calculations.

 

[computer_terminator]

The PFD dead zone is easy to solve.
Just extend the delay time of the reset signal in your PFD. Make sure the UP/DOWN pulse can make the charge pump fully turned on the switch for the charge/discharge current.
I can send you some paper about the PFD.
IF you need it pm me.

 

[paulc]

I have a little experience before. I joined a team to decide 125MHz CRC for ethernet. For some kinds of PD, if the matching of device is not good, there will be no pulse for very small phase difference. So people will put dummy NAND gates to match the delay inside the PD to reduce the dead zone

 

[computer_terminator]

Here is an old paper for the PFD.

Uploaded file: **broken link removed**

 

[freexyz]

Hi,

I am looking for the DLL IP,
where can get it?
include HDL source code.
please help me !

Thanks to advance

 

[paulc]

I also want to know a DLL IP. Please also tell me. Thanks a lot.

 

[AaronDu]

Who can tell me how to design a high speed Digital PLL or give me some data ??

Thank you!!

 

[freexyz]

On 2002-04-07 19:43, AaronDu wrote:
Who can tell me how to design a high speed Digital PLL or give me some data ??

Thank you!!

Hope I have help you.
Best regards.

freexyz

Uploaded file: **broken link removed**