partition your design.. well, regarding the data flow...
However, I think that most important is the well-behaving FPGA platform.
- you can try board-level feedbacked DCM in Virtex4(virtex5 is not available now except proto/es), PMCD etc.
- And drop down the IO voltage.
- reduce the IO numbers between FPGAs (by using serial IOs?)
- impedance matched traces helps somewhat.
- Power integrity is very important.
- use smps and consider heat dissipation issue.
- TCXO? I don't know.
and if possible, design your system in detail and carefully before you assemble your FPGA platform.
if you can offer the timing constaint between the fpgas to board designer then they can help you save your time for rtl-synthesis/pnr.