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"When the PLL is in lock, Clk1 and Clk2 have identical frequency, but their phase difference can show variations. The PLL will try to maintain a phase difference close to zero, as result of the `ideal integrator' functionality of our low-pass filter. Identical frequency means that between every two edges of Clk1, precisely one edge of Clk2 will occur. After an edge has occurred on both Clk1 and Clk2, both left flip-flops are reset by the nand-gate. Only when two edges occur on Clk1 without an intermediate edge on Clk2, the flip-flop in the cycle slip detector will become set. This can only occur if Clk1 has a higher frequency than Clk2."
MSSN and safwatonline,
thank u for ur reply.
The lock detector will be used in a fractional pll.
That means the phase difference between ref_clk and div_out_clk will be large some times due to the
changing div_ratio. I want to have a solution which can detect locking with a certern accuracy.
allow maybe 1/4 or 1/8 ref_clk period phase deviation.
Ok u can use two counters one to count the cycles of the reference clock and the other to count the cycles of the feedback clock and before overflow of the counter that counts the reference clock u compare between the values of the 2 counters which can tell u if u r in lock if they r equal or near lock if there is small difference or away from lock if there is large difference,however this is the basic idea but u have to choose no. of FFs in the counters according to the accuracy u want and ur frequencies and u have to add some logic to adjust the lock detector when the divider ratio changes,there is other ways to make the lock detector but this is a precise and easy method as it is fully digital,good luck