Continue to Site

# How to design a barrel shifter using verilog language?

Status
Not open for further replies.

#### clivechen

##### Member level 3
Hi, everybody
I want to design a barrel shifer in our design, but I don't how to discribe it using verilog language, or it is only can be generated in the synthetize statge?

clive chen

#### Renjith

##### Full Member level 3
verilog has got operators for shift function.
for ex: to shift "A" by 5 towards left, u need to write like A << 5.

#### kaiser

##### Newbie level 5
A barrel shifter has much more functions then a simple shifter.
- selects arbitrary contiguous n bits out of 2n input buts.
- right shift: data into top, 0 into bottom;
- left shift: 0 into top, data into bottom;
- rotate: data into top and bottom.

Here is an example o simple verilog code that's doing a barrel shifter:

module shifter(data,b,result);
parameter Nminus1 = 31; /* 32-bit shifter */
input [Nminus1:0] data; /* compute parity of these bits */
input [3:0] b; /* amount to shift */
output [Nminus1:0] result; /* shift result */

assign result = data << b;
endmodule

#### Dylan01

##### Newbie level 5
This is a very simple behavioral code for 8 bit input data:remember n bit data can be at most shifted by n bits.so you need log2(N) bits in shift control.

module barrelshift(a,b,sh);
parameter N=8;
parameter shift=3; /*equal to log2(N)*/
input [N-1:0] a;
output [N-1:0] b;
input [shift:0] sh;
reg [N-1:0] b;
always @(sh or a)
case (sh)
3'b000: b = a;
3'b001: b = a>>1;
3'b010: b = a>>2;
3'b011: b = a>>3;
3'b100: b = a>>4;
3'b101: b = a>>5;
3'b110: b = a>>6;
3'b111: b = a>>7;
endcase

endmodule

#### umairsiddiqui

##### Full Member level 2
here is a 16-bit shifter in vhdl, you can easily convert it into verilog ;-).....

enjoy my code....(code is provided without any warrenty of any kind....!!!!!)

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity shifter is
port
(
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(3 downto 0);
c_in : in std_logic;
opsel : in std_logic_vector(2 downto 0);
result : out std_logic_vector(15 downto 0);
c_out : out std_logic;
ofl_out : out std_logic
);
end Shifter;

architecture dataflow of shifter is
signal shltemp, shrtemp, saltemp, sartemp, roltemp,
rortemp, rcltemp, rcrtemp, carry_result : std_logic_vector(16 downto 0);
begin
ShiftLogicalLeft: process(a , b, c_in) is
begin
case b is
when "0000" => shltemp <= c_in & a(15 downto 0);
when "0001" => shltemp <= a(15) & a(14 downto 0) & "0";
when "0010" => shltemp <= a(14) & a(13 downto 0) & "00";
when "0011" => shltemp <= a(13) & a(12 downto 0) & "000";
when "0100" => shltemp <= a(12) & a(11 downto 0) & "0000";
when "0101" => shltemp <= a(11) & a(10 downto 0) & "00000";
when "0110" => shltemp <= a(10) & a(09 downto 0) & "000000";
when "0111" => shltemp <= a(09) & a(08 downto 0) & "0000000";
when "1000" => shltemp <= a(08) & a(07 downto 0) & "00000000";
when "1001" => shltemp <= a(07) & a(06 downto 0) & "000000000";
when "1010" => shltemp <= a(06) & a(05 downto 0) & "0000000000";
when "1011" => shltemp <= a(05) & a(04 downto 0) & "00000000000";
when "1100" => shltemp <= a(04) & a(03 downto 0) & "000000000000";
when "1101" => shltemp <= a(03) & a(02 downto 0) & "0000000000000";
when "1110" => shltemp <= a(02) & a(01 downto 0) & "00000000000000";
when "1111" => shltemp <= a(01) & a(00)          & "000000000000000";
when others => shltemp <= (others => '0');
end case;
end process;

ShiftLogicalRight: process(a, b, c_in) is
begin
case b is
when "0000" => shrtemp <= c_in & a(15 downto 0);
when "0001" => shrtemp <= a(00) & "0"               & a(15 downto 01);
when "0010" => shrtemp <= a(01) & "00"              & a(15 downto 02);
when "0011" => shrtemp <= a(02) & "000"             & a(15 downto 03);
when "0100" => shrtemp <= a(03) & "0000"            & a(15 downto 04);
when "0101" => shrtemp <= a(04) & "00000"           & a(15 downto 05);
when "0110" => shrtemp <= a(05) & "000000"          & a(15 downto 06);
when "0111" => shrtemp <= a(06) & "0000000"         & a(15 downto 07);
when "1000" => shrtemp <= a(07) & "00000000"        & a(15 downto 08);
when "1001" => shrtemp <= a(08) & "000000000"       & a(15 downto 09);
when "1010" => shrtemp <= a(09) & "0000000000"      & a(15 downto 10);
when "1011" => shrtemp <= a(10) & "00000000000"     & a(15 downto 11);
when "1100" => shrtemp <= a(11) & "000000000000"    & a(15 downto 12);
when "1101" => shrtemp <= a(12) & "0000000000000"   & a(15 downto 13);
when "1110" => shrtemp <= a(13) & "00000000000000"  & a(15 downto 14);
when "1111" => shrtemp <= a(14) & "000000000000000" & a(15);
when others => shrtemp <= (others => '0');
end case;
end process;

ShiftArithmaticLeft: saltemp <= shltemp;

ShiftArithmaticRight: process(a, b, c_in) is
variable s : std_logic;
begin
s := a(15);
case b is
when "0000" => sartemp <= c_in & a(15 downto 0);
when "0001" => sartemp <= a(00) & s                                                         & a(15 downto 01);
when "0010" => sartemp <= a(01) & s & s                                                     & a(15 downto 02);
when "0011" => sartemp <= a(02) & s & s & s                                                 & a(15 downto 03);
when "0100" => sartemp <= a(03) & s & s & s & s                                             & a(15 downto 04);
when "0101" => sartemp <= a(04) & s & s & s & s & s                                         & a(15 downto 05);
when "0110" => sartemp <= a(05) & s & s & s & s & s & s                                     & a(15 downto 06);
when "0111" => sartemp <= a(06) & s & s & s & s & s & s & s                                 & a(15 downto 07);
when "1000" => sartemp <= a(07) & s & s & s & s & s & s & s & s                             & a(15 downto 08);
when "1001" => sartemp <= a(08) & s & s & s & s & s & s & s & s & s                         & a(15 downto 09);
when "1010" => sartemp <= a(09) & s & s & s & s & s & s & s & s & s & s                     & a(15 downto 10);
when "1011" => sartemp <= a(10) & s & s & s & s & s & s & s & s & s & s & s                 & a(15 downto 11);
when "1100" => sartemp <= a(11) & s & s & s & s & s & s & s & s & s & s & s & s             & a(15 downto 12);
when "1101" => sartemp <= a(12) & s & s & s & s & s & s & s & s & s & s & s & s & s         & a(15 downto 13);
when "1110" => sartemp <= a(13) & s & s & s & s & s & s & s & s & s & s & s & s & s & s     & a(15 downto 14);
when "1111" => sartemp <= a(14) & s & s & s & s & s & s & s & s & s & s & s & s & s & s & s & a(15);
when others => sartemp <= (others => '0');
end case;
end process;

RotateLeft: process(a, b, c_in) is
begin
case b is
when "0000" => roltemp <= c_in & a(15 downto 0);
when "0001" => roltemp <= a(15) & a(14 downto 0) & a(15);
when "0010" => roltemp <= a(14) & a(13 downto 0) & a(15 downto 14);
when "0011" => roltemp <= a(13) & a(12 downto 0) & a(15 downto 13);
when "0100" => roltemp <= a(12) & a(11 downto 0) & a(15 downto 12);
when "0101" => roltemp <= a(11) & a(10 downto 0) & a(15 downto 11);
when "0110" => roltemp <= a(10) & a(09 downto 0) & a(15 downto 10);
when "0111" => roltemp <= a(09) & a(08 downto 0) & a(15 downto 09);
when "1000" => roltemp <= a(08) & a(07 downto 0) & a(15 downto 08);
when "1001" => roltemp <= a(07) & a(06 downto 0) & a(15 downto 07);
when "1010" => roltemp <= a(06) & a(05 downto 0) & a(15 downto 06);
when "1011" => roltemp <= a(05) & a(04 downto 0) & a(15 downto 05);
when "1100" => roltemp <= a(04) & a(03 downto 0) & a(15 downto 04);
when "1101" => roltemp <= a(03) & a(02 downto 0) & a(15 downto 03);
when "1110" => roltemp <= a(02) & a(01 downto 0) & a(15 downto 02);
when "1111" => roltemp <= a(01) & a(00)          & a(15 downto 01);
when others => roltemp <= (others => '0');
end case;
end process;

RotateRight: process(a, b, c_in) is
begin
case b is
when "0000" => rortemp <= c_in & a(15 downto 0);
when "0001" => rortemp <= a(00) & a(00) & a(15 downto 1);
when "0010" => rortemp <= a(01) & a(01 downto 0) & a(15 downto 02);
when "0011" => rortemp <= a(02) & a(02 downto 0) & a(15 downto 03);
when "0100" => rortemp <= a(03) & a(03 downto 0) & a(15 downto 04);
when "0101" => rortemp <= a(04) & a(04 downto 0) & a(15 downto 05);
when "0110" => rortemp <= a(05) & a(05 downto 0) & a(15 downto 06);
when "0111" => rortemp <= a(06) & a(06 downto 0) & a(15 downto 07);
when "1000" => rortemp <= a(07) & a(07 downto 0) & a(15 downto 08);
when "1001" => rortemp <= a(08) & a(08 downto 0) & a(15 downto 09);
when "1010" => rortemp <= a(09) & a(09 downto 0) & a(15 downto 10);
when "1011" => rortemp <= a(10) & a(10 downto 0) & a(15 downto 11);
when "1100" => rortemp <= a(11) & a(11 downto 0) & a(15 downto 12);
when "1101" => rortemp <= a(12) & a(12 downto 0) & a(15 downto 13);
when "1110" => rortemp <= a(13) & a(13 downto 0) & a(15 downto 14);
when "1111" => rortemp <= a(14) & a(14 downto 0) & a(15);
when others => rortemp <= (others => '0');
end case;
end process;

RotateCarryLeft: process(a, b, c_in) is
begin
case b is
when "0000" => rcltemp <= c_in & a(15 downto 0);
when "0001" => rcltemp <= a(15) & a(14 downto 0) & c_in;
when "0010" => rcltemp <= a(14) & a(13 downto 0) & c_in & a(15);
when "0011" => rcltemp <= a(13) & a(12 downto 0) & c_in & a(15 downto 14);
when "0100" => rcltemp <= a(12) & a(11 downto 0) & c_in & a(15 downto 13);
when "0101" => rcltemp <= a(11) & a(10 downto 0) & c_in & a(15 downto 12);
when "0110" => rcltemp <= a(10) & a(09 downto 0) & c_in & a(15 downto 11);
when "0111" => rcltemp <= a(09) & a(08 downto 0) & c_in & a(15 downto 10);
when "1000" => rcltemp <= a(08) & a(07 downto 0) & c_in & a(15 downto 09);
when "1001" => rcltemp <= a(07) & a(06 downto 0) & c_in & a(15 downto 08);
when "1010" => rcltemp <= a(06) & a(05 downto 0) & c_in & a(15 downto 07);
when "1011" => rcltemp <= a(05) & a(04 downto 0) & c_in & a(15 downto 06);
when "1100" => rcltemp <= a(04) & a(03 downto 0) & c_in & a(15 downto 05);
when "1101" => rcltemp <= a(03) & a(02 downto 0) & c_in & a(15 downto 04);
when "1110" => rcltemp <= a(02) & a(01 downto 0) & c_in & a(15 downto 03);
when "1111" => rcltemp <= a(01) & a(00) & c_in & a(15 downto 02);
when others => rcltemp <= (others => '0');
end case;
end process;

RotateCarryRight: process(a, b, c_in) is
begin
case b is
when "0000" => rcrtemp <= c_in & a(15 downto 0);
when "0001" => rcrtemp <= a(00) & c_in & a(15 downto 1);
when "0010" => rcrtemp <= a(01) & a(0) & c_in & a(15 downto 2);
when "0011" => rcrtemp <= a(02) & a(01 downto 0) & c_in & a(15 downto 03);
when "0100" => rcrtemp <= a(03) & a(02 downto 0) & c_in & a(15 downto 04);
when "0101" => rcrtemp <= a(04) & a(03 downto 0) & c_in & a(15 downto 05);
when "0110" => rcrtemp <= a(05) & a(04 downto 0) & c_in & a(15 downto 06);
when "0111" => rcrtemp <= a(06) & a(05 downto 0) & c_in & a(15 downto 07);
when "1000" => rcrtemp <= a(07) & a(06 downto 0) & c_in & a(15 downto 08);
when "1001" => rcrtemp <= a(08) & a(07 downto 0) & c_in & a(15 downto 09);
when "1010" => rcrtemp <= a(09) & a(08 downto 0) & c_in & a(15 downto 10);
when "1011" => rcrtemp <= a(10) & a(09 downto 0) & c_in & a(15 downto 11);
when "1100" => rcrtemp <= a(11) & a(10 downto 0) & c_in & a(15 downto 12);
when "1101" => rcrtemp <= a(12) & a(11 downto 0) & c_in & a(15 downto 13);
when "1110" => rcrtemp <= a(13) & a(12 downto 0) & c_in & a(15 downto 14);
when "1111" => rcrtemp <= a(14) & a(13 downto 0) & c_in & a(15);
when others => rcrtemp <= (others => '0');
end case;
end process;

with opsel select
carry_result <= shltemp when "000",
shrtemp when "001",
saltemp when "010",
sartemp when "011",
roltemp when "100",
rortemp when "101",
rcltemp when "110",
rcrtemp when "111",
(others => '0') when others;

result <= carry_result(15 downto 0);

c_out <= carry_result(16);

-- overflow is defined for 1-bit shift/rotates
process(carry_result, opsel, a) is begin
case opsel is
when "000" => -- sll
ofl_out <= carry_result(15) xor carry_result(16);
when "001" => -- slr
ofl_out <= a(15);
when "010" => -- sal
ofl_out <= carry_result(15) xor carry_result(16);
when "011" => -- sar
ofl_out <= '0';
when "100" => -- rol
ofl_out <= carry_result(15) xor carry_result(16);
when "101" => -- ror
ofl_out <= carry_result(15) xor carry_result(14);
when "110" => -- rcl
ofl_out <= carry_result(15) xor carry_result(16);
when "111" => -- rcr
ofl_out <= carry_result(15) xor carry_result(14);
when others =>
ofl_out <= '0';
end case;
end process;

end dataflow;

### clivechen

Points: 2

#### mrnoone

##### Newbie level 4
here is the simple code for barrel shifter in verilog using muxes:

////////////
module shifter_main(Q,A,C0,C1,C2,Cin,Cout);
input [7:0] A;
input C0,C1,C2,Cin;
output [7:0] Q;
output Cout;
reg [1:0]S;
always @ (C0 or C1 or C2)
if(C0) S=2'b00;
else if(C1) S=2'b01;
else if(C2) S=2'b10;
else S=2'b11;
shifter cct(Q,S,A,Cin,Cout);
end module

//////////////
module Barrel_shifter_main(A,C0,C1,C2,C3,Q);
input [7:0]A;
input C0,C1,C2,C3;
output [7:0]Q;
reg [2:0]S;
always @ (C0 or C1 or C2 or C3)
if(C0) S=3'b001;
else if(C1) S=3'b011;
else if(C2) S=3'b101;
else if(C3) S=3'b111;
else S=3'b000;
barrel_shifter shfter(A,S,Q);
end module
//

The code for the 4x1 MUX used in the Shifter;
module mux(y,d0,d1,d2,d3,s);
input d3,d2,d1,d0;
input [1:0]s;
output y;
reg y;
always @ (d0 or d1 or d2 or d3 or s)
case (s)
2'b00:y=d0;
2'b01:y=d1;
2'b10:y=d2;
2'b11:y=d3;
endcase
end module
//

module mux8x1(y,d0,d1,d2,d3,d4,d5,d6,d7,s);
input d0,d1,d2,d3,d4,d5,d6,d7;
input [2:0] s;
output y;
reg y;
always @(d0 or d1 or d2 or d3 or d4 or d5 or d6 or d7 or s)
case (s)
3'b000:y=d0;
3'b001:y=d1;
3'b010:y=d2;
3'b011:y=d3;
3'b100:y=d4;
3'b101:y=d5;
3'b110:y=d6;
3'b111:y=d7;
endcase
end module

//

module shifter(Q,S,A,Cin,Cout);
input [7:0] A;
input [1:0]S;
input Cin;
output [7:0] Q;
output Cout;
parameter d=1'b0;
reg Cout;
mux mux1(Q[7],A[7],Cin,A[6],d,S);
mux mux2(Q[6],A[6],A[7],A[5],d,S);
mux mux3(Q[5],A[5],A[6],A[4],d,S);
mux mux4(Q[4],A[4],A[5],A[3],d,S);
mux mux5(Q[3],A[3],A[4],A[2],d,S);
mux mux6(Q[2],A[2],A[3],A[1],d,S);
mux mux7(Q[1],A[1],A[2],A[0],d,S);
mux mux8(Q[0],A[0],A[1],Cin,d,S);
always @ (A or S)
case (S)
2'b00: Cout=0;
2'b01: Cout=A[0];
2'b10: Cout=A[7];
2'b11: Cout=0;
endcase
endmodule
//

//The code for the rotator;
module barrel_shifter(A,S,Q);
input [7:0]A;
input [2:0]S;
output [7:0]Q;
parameter d=1'b0;
mux8x1 mux0(Q[7],d,A[6],A[5],A[4],A[3],A[2],A[1],A[0],S);
mux8x1 mux1(Q[6],d,A[5],A[4],A[3],A[2],A[1],A[0],A[7],S);

mux8x1 mux2(Q[5],d,A[4],A[3],A[2],A[1],A[0],A[7],A[6],S);
mux8x1 mux3(Q[4],d,A[3],A[2],A[1],A[0],A[7],A[6],A[5],S);
mux8x1 mux4(Q[3],d,A[2],A[1],A[0],A[7],A[6],A[5],A[4],S);
mux8x1 mux5(Q[2],d,A[1],A[0],A[7],A[6],A[5],A[4],A[3],S);
mux8x1 mux6(Q[1],d,A[0],A[7],A[6],A[5],A[4],A[3],A[2],S);
mux8x1 mux7(Q[0],d,A[7],A[6],A[5],A[4],A[3],A[2],A[1],S);
endmodule

#### shawi99

##### Newbie level 1
hello every body ..can any one tell me what is a code for 8 bit barrel shifter and how its work

Status
Not open for further replies.