How to design a bandgap voltage reference? (basic)

[Fei]

How to design a bandgap voltage reference?

The architecture is the figure 11.20 in Razavi’s book


My target: Trying to find the value of W/L of transistors, Resistance to make this circuit generate a zero TC bandgap reference at 27 degree.

Problem: I can’t get the right result.

Global setting:Vdd=2.5 ; n=8 ; Q3=Q1; all L is identical, W of nmos is identical, W of pmos is identical;

I list down my procedure here, please help to check where is wrong, thank you.

1) Determine VBE0 at temp=27 degree
By simulation, I got the numbers:
When Ie = 10uA, VBE(n=1) =771.3 mV; VBE(n= 8 ) = 716.8mV, so deltaVBE=54.5mV
By calculation, (thermal voltage) Vt*ln8 = 54mV

2) R1 = deltaVbe/I = 5.45K ohm

3) To meet requirement: I=10uA, Vx = Vy at temp=27, and all the transistors should be in saturation region,
Set L=2um, then sweep W of pmos and nmos transistors.
Result: when (W/L)n = 13u/ 2u; (W/L)p = 4u/ 2u; I=10uA, Vx=Vy, drain voltage of M1 and M2 are almost the same.

4) It’s time to calculate R2 value
(R2/R1)* deltaVbe + VBE(Q3) = Vout;
To meet TC_vout | (temp=27) =0, R2/R1 should be around 8.
So, sweep the Resistance Ration from 7 to 8 by 0.1 step, the output shows like
When R2/R1 = 8, it is a increased line as temp increases
When R2/R1= 7, it is a decreased line as temp increases
When R2/R1 =7.5, it is the most flatten curve, then zoom in, I found the following curve, also the voltage is wrong.

 

[cinch]

You get better result (less variation and proper bell curve) if u keep lesser current. Try with 3uA current. Also try keeping emitter ratio=5 and resistor ratio, R2/R1 = 11.6.
Plz try this and share the result.

 

[pfd001]

It seems that your bandgap is negative temp effect. You can increase the R2/R1 by smaller step from 7.5

 

[ipsc]

Hi Fei,

can you please specify what do you mean by "I can’t get the right result"?

Do you mean curve is not correct or the bandgap voltage is not correct?

Regards

 

[gunturikishore]

I doubt your amplifier liner operation. Make usre that the two inputs to the amplifier are always very near to each other. You need to shift the slope also. Adjust the resistor accordingly and transistor ratio.

 

[aryajur]

Hello Fei,
n=8 is a good choice since when you decide to layout the circuit, n=8 will provide better matching of your parasitic bipolars. The main purpose of M1, M2, M3 and M4 is to keep the voltages at nodes X and Y same and also have the same currents in both the branches. For this the Vgs of M1 and M2 must match for this make the W/L ratio of M1 and M2 large. The purpose of M3 and M4 is to match the currents in the 2 strings, for that the W/L ratio of M3 and M4 should be small.
To design the circuit follow these steps:
1. Detemine the current you want to allow based on the power consumption allotment. - I (at 27 deg)
2. Once you know the current calculate R1 = Vt/I *ln8
3. Simulate a temperature coefficient of a Bipolar (one you will use for Q3) over the entire temp range - choose an average value of this temperature coefficient say its -2mV/K
4. If your temperature range -40 to 125 then you may want the temp coefficient to cancel off at 50 deg C. So set the Vbe temp coefficient at 50 deg C = R2/R1 Vt ln8 at 50 deg C.
5. Now simulate. You should get a fairly nice curve. Adjust R2/R1 to minimize the variation.

That should do it.

One thing to look at is the current range. The current in the strings is PTAT. The maximum current flowing in the strings will be Vt*ln8 / R1 evaluated at your highest temperature of interest. Make sure that at that current and W/L ratios of M1-M4, none of them goes into triode region of operation at that temperature (Vth also decreases slightly with temperature)
For the value of voltage, the exact voltage at which you will get low temperature coefficient, would determine your bandgap voltage and it may not necessarily be exact 1.2V but will be a little off, depending upon your Bipolars, etc.
One good way of determining if its the temperature coefficient control or the current mirroring circuit that is causing the problem is to plot the voltages at X and Y. They should be the same(almost) and should remain that way throughout your temperature range. If not one of M1-M4 is going out of threshold.
Hope this helped.

 

[sissi]

hi,aryajur
you talked about the fundamental that chose current of the circuit. should we consider the noise,such thermal noise?should we choose how much current if we conside the thermal noise?
reguards
sissi

 

[aryajur]

If thermal noise level seems to be an issue, you can always consider filtering it out using a RC filter at the bandgap output. That may be helpful for your PSRR as well.

 

[mind1985]

You can find a lot of info in Baker CMOS Circuit Design, Layout, and Simulation