Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
i have already designed it through transmission gate but the problem is
2GHz frequency and CL= 2pF
i am getting the distorted output
wat should be the (w/L)of the transistors.
do u know how to calculate the (W/L)'s of the transistors?
but the problem is i have made the deign of 8:1 mux using transmission gate
without loading effect.
now when i am including CL i am not getting the output.
so wat to do.
n one more thing how do i choose my w/l
that is how to calculate W of a transistor.
You can design a basic transmission gate mux and do its layout. Extract the netlist from the layout. Then you can use the sweep command in spice to vary the width of the transistors and the run the simulations for all the widths and get the width that matches your specifications. The only drawback in this method is that the effect of capacitances for each varying width cannot be mirrored. But this method will give you an approximate idea of the width.