mdcui
Advanced Member level 4
- Joined
- Aug 23, 2005
- Messages
- 107
- Helped
- 29
- Reputation
- 58
- Reaction score
- 5
- Trophy points
- 1,298
- Location
- california, USA
- Activity points
- 2,078
does anyone know how to design a differential buffer( the first stage of an input buffer) that deals with differential clock signal, the requirements are:
1. high speed, delay should be within 0.5ns
2. zero static power, which means that when two input are stay at VIH and VIL respectively, there should be no static current
3. 1.8V vcc supply
thanks a lot.
1. high speed, delay should be within 0.5ns
2. zero static power, which means that when two input are stay at VIH and VIL respectively, there should be no static current
3. 1.8V vcc supply
thanks a lot.
