How to design 1 to 8 multiplier

[kunal1514]

Hi all,

How to design 1 to 8 multiplier

 

[ebuddy]

Manually, you can either write the boolean table and design the logic, or you can design 1 to 2 mux and cascade them together. Of course, an HDL approach is most effecient.

 

[cherin]

module mux_8to1(sel,out,inp1,inp2,inp3,inp4,inp5,inp6,inp7,inp8);

input [2:0] sel;
input inp1,inp2,inp3,inp4,inp5,inp6,inp7,inp8;
output out;

assign out=(sel[2]?(sel[1]?(sel[0]?inp8:inp7)sel[0]?inp6:inp5))sel[1]?(sel[0]?inp4:inp3)sel[0]?inp2:inp1)));

endmodule


this is the verilog module for an 8 is to 1 mux
As already mentioned, an alternative is to use 7 2:1 muxes in a binary tree structure to make up an 8 is to 1 mux.
Hope this is useful, Cheers!