how to desgin a startup for bandgap reference?

[bharatsmile2007]

transbrother

hi all,

what are the design limitations for startup circuit in BGR?

how to improve the startup time using the below circuit?

Attachement is the Conv BGR and the startup i want to desgin....

 

[transbrother]

bandgap reference startup

Hello bharatsmile,

Limitations of this startup that I can think of:
1. it is always on because when vdd is up, the diode connected nmos is going to have a vgs across it. The pmos connected to V- will have a high Vgs across it.
2. the bandgap voltage is going to have an error term because the startup pmos transistor has current that dumps into V- node causing a mismatch of current between Q2 and Q1.
Question:
1. Are you relying on the pmos in the startup ckt whose gate is connected to Vc1 to pull up its drain? I think you'd have to burn a lot of current to pull on its drain and hence shut off the pmos start transistor whose drain is connected to V-.

If you are still planning on using this ckt for startup then you can do the following to increase startup speed:
Make sure your amp has a high bandwidth and starts up at lower voltages. This is because you seem to be relying on the amplifier to pull down on Vc1 during startup. so, if you pull down vc1 at a lower voltage and at a faster rate, your startup will be enhanced.

 

[xy85061182]

Maybe you can use a long L NMOS in the startup circuit.

 

[bharatsmile2007]

Thanks xy85061182..

what is the advantage of using Long L NMOS for the startup?

FYI:i have named the transistors in the updated attachment...

 

[bharatsmile2007]

Thanks Transbrother for ur reply..


FYI:I have uploaded the attachement(named the transistors for startup)

Limitations:

1)i adjusted the vgs of MS2 transistor so that it goes to cutoff when power supply reaches VDD...but sitll i can see nano amps current following through it...

Questions:

1)yes transbrother,i need burn some current in MS1 transistor to bring MS2 to cutoff...

I will try to improve upon the opamp and check...

do u suggest any other start up circuits...?

Thanks again...

 

[transbrother]

bharatsmile,

It looks like MS3 is a low W/L device because its vgs needs to be high enough to turn MS2 off.

I dont find anything particularly wrong in the startup circuit except that your condition to turn MS2 off could result in wasting some current. What i do like bout this ckt is that there is no startup loop.

What xy85061182 might be talking about is that people usually use a 'long channel' transistor for startup. So in this case you'll have to use a long channel pmos transistor (grounded gate) instead of MS1. Since this active load (long channel) transistor rises with Vdd one can then process signals in such a way to pull down Vc1 then turn this pull down path off when the currents have reached a certain levels. The problem with such an approach is that you have a feedback startup loop in addition to the ptat and the bandgap loops. This approach could be faster as you are using feedback. However, the risk is that the loop might oscillate.


Another very simple idea might be to just put a big resistor (or an active load like a long channel transistor) from Vc1 to gnd without this startup ckt that you have. That way there will always be a pulldown from Vc1. When there is a sufficient Vgs on M2 and M3, they will conduct current startup the loop. And, as long as the amp can source the current to satisfy the load at Vc1, you should be fine during regular operation. If you are trying this solution please let me know how it works out. Also this approach might give a faster startup as you are not relying on the BW of a startup ckt per say.

However, I do think that the general startup idea you have is correct. That is pulling down on Vc1 to startup the ckt.


I am not sure if you are planning to build silicon using this circuit. One concern I would have in your circuit is that you are using a nmos (MS3) Vgs to turn off a Pmos (MS2). That is you are trying to match an nmos vgs to that of a pmos. So, I would substitute the MS3 to a diode connected pmos. That way the Vt of the MS2 and the pmos MS3 would track.

As for the nano amps of current in MS2, you'd probably just have to adjust your MS2 and MS3 sizing to tackle that if you want to use this circuit.

 

[saro_k_82]

Touching V+, V- nodes for startup is not recommended. A small offset current at V- could provide drastic change in curvature. This method also involves startup loop and you need to be careful that the startup current does not go on-off at steady state. The other minor problem is the lowering of supply rejection.
The standard method is to bring VC1 down. The methods with startup loops can work with very low currents, but need careful investigation. If you want to be safe don't introduce startup currents in to V+/V-.

 

[bharatsmile2007]

Thanks transbrother and saro_k_82 for the points...

The use of startup circuit is to avoid the undesirable operating point in the circuit.Is it that startup circuit also helps in bringing up the bandgap voltage quicker?

 

[bharatsmile2007]

hi,

i have one more doubt:

will there be any difference in output reference voltage (bandgap reference) with startup circuit and without startup circuit?

Thanks...

 

[bharatsmile2007]

hi,

would pls let me know what need to be the initial condition for the nodes to test the startup ciruit?

FYIls find the circuit with nodes labeled...

Thanks a lot....

 

[transbrother]

bharathsmile,

answer to where vbg will be different with and without startup:
If the circuit has started up, and vbg comes to the right voltage, taking the startup out of the picture should not change vbg.

On initial conditions:
Ramp up Vdd from gnd. Try different rise times. And, transient sims.

The reason it is not a super idea to give intial conditions is that it could vary and be significantly different in silicon. If you want to perform a quick simulation then try the standard initial conditions. i.e:
V- = 0, V+ = 0; This is kind of justified because there should be no current flowing thru

Added after 16 seconds:

flowing thru Q2 and Q1

 

[bharatsmile2007]

Thanks Transbrother...

when i set the initial conditions V- and V+ to zero without start up circuit and perform DC (.op) sim, i see no current flowing ,all the transistors are in cut off,which is the undesirable condition.

when i set the initial conditions V- and V+ to zero without start up circuit and perform tran sim,with VDD ramp, i see the BGR builds up the voltage and settles to 1.2V

My doubt is how to set the circuit to unwanted operating condition by using initial conditions then perform the transient simulation and see the BGR failing to build up the voltage?

 

[transbrother]

THe reason that the transient is starting up is probably because you have some leakage current path into V- and V+ starting up the ckt. You could put an ideal current source of 100nA to gnd pulling down on V- and V+ and turn this current off later. That way you'll ensure that V- and V+ is at 0V during transient startup.

So in this case if the startup ckt starts up properly, it should overcome the 100nA of current and still startup the circuit. This would test if the startup ckt is doing its job.

 

[bharatsmile2007]

Thanks transbrother...its working i can see the difference with startup and without startup in transient simulation...

i have one more question:

when i did DC(.op) simulation with startup circuit,with no initial conditions, i saw the MS1 is in linear,MS2 cutoff,MS3 sat.Is there any problem if MS1 is in linear,i mean any disadvantages?


i will simulate and let u know the results for the suggestion u gave:

"Another very simple idea might be to just put a big resistor (or an active load like a long channel transistor) from Vc1 to gnd without this startup ckt that you have. That way there will always be a pulldown from Vc1. When there is a sufficient Vgs on M2 and M3, they will conduct current startup the loop. And, as long as the amp can source the current to satisfy the load at Vc1, you should be fine during regular operation. If you are trying this solution please let me know how it works out. Also this approach might give a faster startup as you are not relying on the BW of a startup ckt per say."


Thanks again..

 

[transbrother]

AFter startup and in normal operation, MS1 has to be in triode region in order to turn MS2 off. If MS1 is in sat, MS2 will not turn off properly. The disadvantage is that current thru MS1 will not match current thru M2 or M3. However, the MS1 current will be lower than Id of M2 or M3. This is the characteristic of the startup ckt. However, it is important to note that during the startup procedure MS1 is in sat when the ckt is starting up.

 

[bharatsmile2007]

Thanks transbrother...

i have one doubt..

The use of startup circuit is to avoid the undesirable operating point in the circuit.Is it that startup circuit also helps in bringing up the bandgap voltage quicker compared to without startup?

 

[transbrother]

Bharathsmile2007,

If one cannot bring up the bandgap voltage unless a startup ckt is present then we cannot compare the case of bandgap voltage coming up with and without the startup ckt. Having said that, the startup ckt together with the amplifier and other ckts here that are involved in the startup constitute the startup time. EVen if you are able to have an ideal startup ckt (that responds to vdd and produces the desired output in 0 sec), you will still be limited by the response of the ptat loop, op amp, and transistors in the bandgap circuitry to turn the startup ckt off.

hope this helps.

-Transbrother

 

[bharatsmile2007]

hi transbrother..

thanks for the info...The point u mentioned is correct...we cant compare the settling time...

i did two types of simulation for seeing the settling time in different corners...

1)Did tran (VDD ramp) without initial conditions for BGR with startup and without startup.

2) Did tran (VDD ramp) with initial conditions for BGR with startup and
without startup.(initial condition Vc1 to VDD)

In 1st case i see the settling time for BGR with startup is late compared to without startup...(the difference is less..but late with startup..)

In the 2nd case i see the settling time for BGR with startup is early compared to without startup...(this is what u told it cant be compared..because with initial conditons and no startup in worst corner BGR is not able build the desired voltage but in the same corner with startup BGR is able to build the desired voltage...)

Is that in the 1st case also the settling time for the BGR with startup should be early compared without startup?

Thanks again...

 

[transbrother]

Bharathsmile,

it is hard to say in your study whether the startup time should be lower with or without the start up circuit. From what I understand of your findings, analyzing case 1, you are able to get the bandgap started up without the startup ckt. That means that there is some startup mechanism (either due to leakage currents or some other method). You need to first understand this mechanism. Then you should be able to compare why the bandgap starts up faster without the startup ckt.

Let me know of your findings.

-Transbrother

 

[bharatsmile2007]

Okie Transbrother..

i will be posting u the updates...