how to descripe a rom with std.textio in vhdl?

[honeyleabe]

vhdl textio

the code is below.when i simulation,read file fail.why?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
library std;
use std.textio.ALL;

entity rom is
Port ( read : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
dout : out STD_LOGIC_VECTOR (15 downto 0)
);
end rom;

architecture Behav of rom is
subtype word is std_logic_vector(15 downto 0);
type memory is array(0 to 65535) of word;
signal adr_in:integer range 0 to 65535;
FILE romin :text is in "rom16.in";
begin
process(read,adr)
variable rom:memory;
variable startup:BOOLEAN:=TRUE;
variable lin:line;
variable j:integer;
variable output : STD_LOGIC_VECTOR (15 downto 0);
begin
if startup then
for j in rom'range loop
readline(romin,lin);
hread(lin,rom(j));
end loop;
startup:=false;
end if;

adr_in<=conv_integer(adr);
if (read ='1') then
output:=rom(adr_in);
else
output:=output;
end if;
dout<=output;
end process;
end Behav;

thanks for your attention