How to describe the macro IP when synthesizing

[xiongdh]

When synthesizing TOP module in DC,U1 is a submodule in TOP.U1 is a IP from other vendor and have the spec document and a verilog behavioral description file that can’t be synthesized.Also the library file and db file can’t be get from the vendor.
More attribute of U1 is described in the following diagram.
(name)(I/O)(driving)(load)(delay from port to DFF)(delay from DFF to port)
in1 in __ 10*NAND2X1/A 3 ns ___
out1 out 1*NAND2X1/X ___ ___ 5ns
****
the submodule U1 has one input in1 ,it drive just 10*NAND2X1/A and the path from U1/in1 to DFF/D is about 3 ns delay. one output out1, it's drive capacity just like 1*NAND2X1/X and the path from DFF/D to U1/out1 is about 5ns delay.
*******
Note: NAND2X1 is a library cell and have 2 input, A is one of the two input and a output X.
When synthesizing the design TOP. The U1.v file that only have the port description of cell U1 is read into DC.the attribute don’t_touch is set for U1 cell.The attribute of U1 in the above diagram need to be described or set when set constrain for the design TOP. Now the question is how to set the constrain or describe U1 before synthesizing.
Maybe a db file that described the attribute of U1 can be built,this is one way to deal this problem,But if I don’t do like that.How can I resolved this problem in another way.

 

[visualart]

Firstly, you may synthesis the top that included the U1,
secoindly, extract the constrain on the U1 from the Top db
So, you shall get the description on the U1

 

[xiongdh]

I want to synthesizing the TOP module ,it has submodule U1 and also other submodule.
U1 is an analog module that don't need to be synthesized. But the property of U1 can affect other submodule when compile in DC. How to build model of U1.