kimjin
Member level 3
the 2fsk signal is :s(t)=sin((2*pi*60000000+a(t)*700000)*t),and 67m is '1',53m is '0'.
i need to design the demodulate circuit .
i look for the demodulate chip, but the the chip's f0 which finded in web is too low ,just khz. and the all digital pll need a very high frequency clk which maybe 600m, my fpga cann't work in that frequency.
i want to find a simple and with a better performance 2fsk demodulate circuit.
how can i do?
thank you!
i need to design the demodulate circuit .
i look for the demodulate chip, but the the chip's f0 which finded in web is too low ,just khz. and the all digital pll need a very high frequency clk which maybe 600m, my fpga cann't work in that frequency.
i want to find a simple and with a better performance 2fsk demodulate circuit.
how can i do?
thank you!