[SOLVED] how to define two or more synthronous clock with same/different setup# in DC

[layowblue]

Hi all

In my design, I have two types of clocks:
input clk;
input [7:0] channel_clk;
They are synchronous clocks, except that "channel_clk" is gated under some conditions by clock_gating cells.
1) When creating sdc, how do I tell the synthesis tool that these two clock types are synchronous to each other?
2) If I want to put tighter setup constaints on channel_clk, what should I do?
3) Some other input pin(say A) goes to flops clocked by both those clocks, how should I specify the input delay for A?

Thanks a lot
Leo

 

[sharath666]

1)Just define them identically
2)Specify more stringent input delays, clock uncertainties etc...
3)Got to think about it....No answers currently...

 

[layowblue]

Hi sharath666

Could you elaborate exactly how to "define then identically"?
I don't think create two(or nine) new clocks with same waveform settings mean that these clocks are synchronous.
Can you put a simple sdc tcl example here?

Thanks
Leo

1)Just define them identically
2)Specify more stringent input delays, clock uncertainties etc...
3)Got to think about it....No answers currently...

 

[sharath666]

I am thinking that should suffice as solvnet says ". The first time in the list is a rising transition, typically the first rising transition after time zero" for the waveform option.

 

[rca]

If "channel_clk" vector are a clock gated version of "clk", you only need to declare one clock source for "clk", the channel_clk vector is covered.
The clock tree tool will go through the clock gated cells and equilibrate all of these branches.

 

[layowblue]

Hi rca

The problem is that channel_clk is 8-bit input pins. As a hardmacro block, we need to synthesis this subblock as a whole deliverable.
Then toplevel "might" gate the "channel_clk" if necessary.

With that said, channel_clk has to be declared in a way that the synthesis tool can understand its synchronous association with "clk".
I found "channel_clk" constraint missing because I see unconstrained datapath in syn reports.

Please help me out..

If "channel_clk" vector are a clock gated version of "clk", you only need to declare one clock source for "clk", the channel_clk vector is covered.
The clock tree tool will go through the clock gated cells and equilibrate all of these branches.

 

[rca]

The SDC command create_clock has the argument "-domain", if the name is the same, that will indicate the clocks are synchronous.

 

[rahul.achates]

you can declare channel clock as create_generated_clock , with source clock "clk" , this will built a relationship between clk and channel clk ..

 

[layowblue]

Thanks rca and rahul.
It turns out both "domain" and "create_generated_clock" work, according to my synthesis result.
Marking it as resolved.

 

[rahul.achates]

Good to know that