Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Well, DC offset is one fundamental limit, but since the latch is allowed only a limited time to resolve the input, you should also consider the minimum input amplitude that will cause it to settle to the full swing within a limited time.
Latch structure has infinite DC gain.But Latch has large random offset.As a example,we will use preamplifier for the latch and its random offset can be cancelled by the preamp.You should arrange the settling time seperately for the preamp and the latch to get the smallest settling time.You can find some solutions from a paper by P.R.Gray.But I cannot recall its name clearly.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.