How to define max_fanout max_transition max_capacitance ?

[roger]

max_transition

Dear:

How to define max_fanout/max_transition/max_capacitance
in the design, please give me some advice or experience.


B.R

 

[farmerwang]

max_fanout

You don't need to, if there is any, should have been defined in the techonology library. Sometime you might want to set max transition transition constraints for performance purpose.

 

[roger]

max_capacitance

Dear:

How to define max_fanout/max_transition/max_capacitance
in the design, please give me some advice or experience.


B.R

I mean set these constraints

 

[nand_gates]

max_transition

Design rules are provided in the vendor technology library
to ensure that the product meets specifications and works
as intended. Typical design rules constrain transition times
(set_max_transition), fanout loads (set_max_fanout), and
capacitances (set_max_capacitance). These rules specify
technology requirements that you cannot violate.
(You can, however, specify stricter constraints.)

For more info please see DC user guide!

 

[visualart]

max_transition dc

The max_fanout/max_transition/max_capacitance is limited in the library. It is a hard limiting.
In the design, you may limit them in the max range.
such as , need the high frequency , you may limit the max fanout < 4(3), max_transition < 1/10*cycle peroid, max_capacitance < 4 unit cell area.

 

[roger]

max fanout limit

The max_fanout/max_transition/max_capacitance is limited in the library. It is a hard limiting.
In the design, you may limit them in the max range.
such as , need the high frequency , you may limit the max fanout < 4(3), max_transition < 1/10*cycle peroid, max_capacitance < 4 unit cell area.

1. 4(3) means 12?
2. max_capacitance < 4 unit cell area, sounds so strange? can you explain it more detailly?

TKS

 

[semi_jl]

max_fanout max_capacitance library why

The value of these parameters is from the library you adopted, and it have no relevancy with your design, but you could set a stricter value according your design.

 

[free1983]

what is meant by max capacitance

Typical design rule scenarios are
• set_max_fanout and set_max_transition commands
• set_max_fanout and set_max_capacitance commands
Typically, a technology library specifies a default max_transition or max_capacitance, but not both. To achieve the best result, do not mix max_transition and max_capacitance.

 

[jcchan]

drc max_transition

You can edit the target library for example vi tsmc25_typ.lib and you will see many table in library, the two dimionsation of table is transition time and load capacitance, so accroding to your timing you can to define what capacitance, transition is good for your design.

 

[jjww110]

drc max_capacitance

if you use command report_constrian in dc,you can get drc of tech lib

 

[yuenkit]

max_fanout default

you need the syntax or the figure?

normally, inside ur tech library, the values are there.

if u define a value which is lower than the one in the library, DC will jst ignored.

That means, the value should always stricten than the one in library, or it will be ignored by DC.

 

[wkong_zhu]

max capacitance and max_fanout constraints + asic

I use set_max_transition in my design to decrease power consumption.

 

[yuenkit]

what does max_transition signify

wkong, why limiting the set_max_transition will help to reduce power-consumption?

 

[wkong_zhu]

how to define max_fanout

I think the more transition time is, the more duration NMOS and PMOS are both working and large current will last more time. so Power is much more in transition time.

 

[yuenkit]

clkbuf max fanout

I thought set_max_transition cause the design use cells with stronger driving-strength,which in turn consume more current

Have you verified your statement with report_power? or it is a general practice in industry?

 

[wkong_zhu]

max_transition - why is this limit given

Just by practice, not theory. It depends on your design and Standard Cell library.