How to define an internal clock in DC?

[liwei039]

clock mux

I just want to define an internal clock in DC. this clock is come from a mux of two input clock then through a combination logic.

should be use create_generate_clock? how to use it?

 

[aravind]

yep use create_generated_clock command

 

[hfooo1]

the two clocks work coinstantaneously or not?

in either situation i dont think it's needed to define a clock.

 

[dcreddy1980]

As you said, the clock is an output of mux, basically i would use a case analysis on the select signal and select which ever clock u want for the optimization, its a better scenarion in your case.

if you have two clocks lets say clk_a and clk_b as inputs to mux, clk_a is connected to select(0) pin of mux and clk-b is connected to select(1) of mux, if you want to optimize the block with worst scenarion where u feel the block can be made robust, then select a high speed clock.

set_case_analysis 0 [get_ports select]
// assumed mux select to be input or define the hierarichal path and now ith above command, it will select clk_a for the analysis

 

[xiongdh]

for syntheisi.You can only defined the fast clock

 

[dechen]

sometimes you may want to define a new clock at the mux output, so a new clock tree can start from the new clock. For synthesis it does not a difference, but it maybe useful for clock tree synthesis.