[SOLVED] How to define a VHDL component and package?

[Hugo17]

Below I do have following two VHDL files. The file x.vhd with a component x which needs to be referenced (included) in the file top.vhd as a package.

-- x.vhd

	library IEEE;
	use IEEE.std_logic_1164.all;
	use IEEE.numeric_std.all;

	package x_pkg is
		component my_x
			port(clk_clk          : in  std_logic    := '0';
				 reset_reset_n    : in  std_logic    := '0';
		end component my_x;
	end package x_pkg;

	-----------------------------------------------------------------------------

	library IEEE;
	use IEEE.std_logic_1164.all;
	use IEEE.numeric_std.all;

	entity x is
		port (
			clk_clk               : in  std_logic         := '0';             --                             clk.clk		
			reset_reset_n         : in  std_logic         := '0';             --                           reset.reset_n
		);
	end entity x;

	architecture rtl of x is

This package needs to be referenced in following top-file:

-- top.vhd

	library ieee;
	use ieee.std_logic_1164.all;

	library altera;
	use altera.altera_syn_attributes.all;
	use work.x_pkg.all;

	entity EyeTracker_Top is
		port
		(
			Nios_Clk : in std_logic;
			Nios_Reset_n : in std_logic;
		);

	end EyeTracker_Top;

	architecture struct of EyeTracker_Top is

	begin
	M1 : my_x port map(Nios_Clk, Nios_Reset_n);            -- Here I get the error message!

After compiling, it get following error message:

Error (12006): Node instance "M1" instantiates undefined entity "my_x"

What is the problem here? I guess there is something wrong with the package reference and/or the libraries (not) included in the project. In the project file I have both files included (top at the bottom). Under "Project Libraries" the path to my work-folder.

Thanks!

 

[TrickyDicky]

the entity is called "x". The component also needs to be called "x". What a component does is create a black box for the compiler to latch on to until the component is matched with the entity during the mapping.

Much better to use direct instantiation. Then you dont need to use components at all. You can instantiate entities directly:

M1 : entity work.x port map(Nios_Clk, Nios_Reset_n);

This way, the compiler checks the port map against the entity. You avoid any missmatches between the entity and component this way, and you'll find out immediatly, rather than waiting for the mapping to complete (which in large designs can take many minutes).

 

[Hugo17]

Direct instantiation is much, much easier!! It also fixed the problem I had :thumbsup:

You saved my day - thanks a lot !

:clap::clap: