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How to decrease the current consumption of the digital gates from the standard cell?

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safwatonline

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how to decrease the current consumption of the digital gates from the standard cell?
 

leeenghan

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current consumption

Hi,

1. Gate the clock to FF

2. Try to make the inter-connect shorter

3. Use lower Vdd

Regards,
Eng Han
 

    safwatonline

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blastronics

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Re: current consumption

1. Avoid unconnected inputs, connect this either to ground or Pulled up.
2. Use low power type IC.
3. Use CMOS instead of TTL type.
4. Use high R pullups. ex. use 10k instead of 1k.
 

safwatonline

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current consumption

actually i am want some non-traditional methods to decrease the current in digital gates in a specific IC technology say 0.18um and 1.8V and having an already made standard cell on 0.18um
 

ieropsaltic

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Re: current consumption

I'm not sure,but you may try decreasing the sizing of both the PUN and PDN of the standard cells (if you're using standard CMOS) .But this would trade-off with your circuit's speed .
 

sp

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current consumption

I am not sure on which foundry of 0.18um u gonna use... but i guess there are few types of transistor u can use to reduce the AC/DC leakage...

what i meant is those low power or thick oxide type of transistor instead of those general type... normally u need to trade off leakage for performance... for instance, when switching, the AC leakage is the Idsat current... reducing W/L will reduce AC leakage but reduce speed/driving strength...

btw, i guess u are talking about standard cell, i dunno whether it can be modify... haha sorry... I am not really onto standard cell...

sp
 

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