[SOLVED] how to declare a bidrectional bus in verilog

[blooz]

suppose if the bidirectional bus is

inout bus_bidir[7:0]

with enable signal en
is it possible to use the bus_bidir alone to make the data transfer in both directions

if en=1 the bus to be used as output

and if en=0 the bus to e used as input .

 

[j_andr]

quite simple:

assign bus_bidir = en ? data : 8'hZZ;
wire [7:0] internal_bus = bus_bidir;
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