How to decide the operating frequency of a design ?

[imbichie]

Hi all,

For an FPGA design, at the time of RTL coding, on what basis we calculate the maximum operating frequency..?

Means before synthesis and critical path analysis, how we ensure that the design will work up to a desired frequency..?

For example initially i have a design which will works an operating frequency of 40 MHz, then now i wants to work the same design with 100 MHz, then how can i ensure that it will work at 100 MHz, before going to the synthesis process...?

 

[kingslayer]

Do you think is this really possible??

How does the tool know the critical path without going through synthesis? Maximum frequency is computed after critical path has been calculated, i.e. after you have the netlist. At source-code level you do not have such information, unless you do some iterative back annotation, but in this case this means that you already went through synthesis.

Cheers

 

[imbichie]

Hi kingslayer,

Thank you for your reply...

So if there is a design which is working at 40 MHz frequency, and we now need to works the design on 100 MHz, in that situation we should make the constraints for 100 MHz and go for synthesis. Then only we can make a decision which will works or not, and we cant decides it during the simulation... Am i right..?

 

[kingslayer]

Dear imbichie,

you are correct. In fact, synthesis is a timing-driven process, so optimization and restructuring of registers and whatsoever is done with the timing optimization in mind. During simulation you check only functionality of the modeled circuit.

However, please anyone with more experience correct me if I am wrong :grin:

Cheers

 

[imbichie]

Hi kingslayer,

Thank you for your reply...

Yes during the rtl simulation there is no timing analysis we are performing.

But during the rtl coding can we get the delay means the combination delay of each path..??
Means an we get the thing combination delay by converting the rtl code in gate level analysis and finding the longest path by means the counting gate stage , then if we know the delay of each gate, then can we calculate the maximum delay offered by that path and can we get the combination delay of that particular path..?

Is it possible..?

 

[kingslayer]

This will only be available after synthesis, otherwise where do you get gate-level paths from?? The procedure you are talking about, i.e. sum up gate-level delays to form the path delay, is what a synthesis tool does :wink: This means: you have to do synthesis.

Cheers

 

[imbichie]

Hi kingslayer,

Thank you for your reply...

can we manually make the gate level model of the combinatorial path and make the above analysis our self...?

Just like if there is an " AND " then we can put an AND gate and all...

Is that possible...?

 

[kingslayer]

Hi imbichie,

Well, if you are able to make the gate-level model by hands you can certainly do whatever analysis you need. For instance, if you have the table of truth of the function you want to realize, you can at first perform network synthesis using classical digital design methodologies. However, I would say that this only works for veeeeeery simple circuits with only a few combinational levels! But in this case you will lose all the advantages of automatic tools: complexity, cost (time), correctness (you should also verify that your "by-hands approach" is valid), reproducible results...

Can I ask you what is your design about? And why are you so afraid of synthesis? :grin:

Cheers

 

[imbichie]

Hi kingslayer,

Thank you for your reply...

Actually this question was asked by an interviewer to me, at that time i cant answered it. Also they had said that its possible during the rtl level coding itself, means before going to the synthesis...

So that is why i posted the question here and discuss the possibilities..

Anyway again thanks for your reply and thanks for giving valuable information and discuss the things with me...

 

[mrflibble]

You can try to design for a maximum number of logic levels. That is, if you can design such that you have only say 1 or 2 logic levels maximum AND can make sure that the routing distances are not too big ==> pretty good timings.

So you can get a rough estimate by guessing your max logic levels, and guessing the placement and then guessing the max delay... But in reality it is bound to become an iterative process where you do your best guess at a design fitting the requirements, and then plug it through synthesis.

Either that or you already had some experience with a similar module on a similar fpga, and then you use that as a starting point. But any large module for something you never made before ... all I can think of is just make it as good as you can think of given the requirements and then verify.

But yeah, for trivial designs you can pretty much predict what the tools are going to spit out in terms of max frequency. I by trivial I really mean trivial. As soon as the module becomes a bit big you never know what the tools are going to come up with to ruin your day this time. I'm looking at you, XST! @_@