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By default, the synthesis tools such as Design Compiler will synthesize your RTL coding according to the fanout requirements of your techonology file(you can refer to your techonology file). Often, for the accuracy and P&R, we can set a smaller fanout limit than that in the technology file so that you can obtain a faster circuit and less area and routing congestion( please note the cell-based P&R, if using a very large one instead of several smaller ones the routing is not so easy and good). Aditionally, you should set the output pins' fanout/capacitance value according to the context environment of your design which should be perceived of during the design division process. Finally, if considering the pads, then you should ask some infomration from your system designer who will give some requirements about the pads such as the input delay/capacitance on the pads and output delay/capacitance on the output pads and so on.