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How to decide the clock frequency in any design?

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mujju433

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On what basis we decide the clock frequency in any design???
 

jasmin_123

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frequency

Keep it at minimum if you like to minimize the dynamic power consumption.
 

shavakmm

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Re: frequency

there are several factors. Important of them are:
1) Input and output data rate : for example if you are designing any encryptor or decryptor you need minimum 100 MHz;
2) Power: Higher the frequency more the power consumption
3)Accuracy of the results required: If higher accuracy is not needed RC oscillator can be used which saves area... and everything we want in compact size..... but RC cant produce higher frequency !
4) Technology: Lower the node more speed (also more power....again trade off !!).... how much fast we want ?
5) Target platform: Is it FPGA or custom ASIC.... naturally ASIC can give higher clok frequency... but FPGA frequency of operation is limited by several other factors

rgds murali
https://asic-soc.blogspot.com
 

cooldude040

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frequency

How do we compensate these things?

Added after 1 minutes:

Is that anything related to combi delays I mean can we decide the frequency by considering all the combinational logic in a Semi custom asic?
 

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