Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to decide PLL LoopBandwidths?

Status
Not open for further replies.

option318

Newbie level 5
Newbie level 5
Joined
Aug 3, 2007
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,330
Who can tell me, how to decide PLL LoopBandwidths?please tell me thanks.
 

the loop bandwidth should not exceed 1/10 of the input frequency.It should be decided based on whether your input noise is dominant or whether your VCO noise is dominant. For input noise you need keep a low bandwidth, for vco noise a large bandwidth is needed to cut it off. Another factor is the lock time , though you can still keep a low bandwidth and lock faster using loop bandwidth enhancement techniques to settle faster.I would suggest you to refer the thesis available on PLL's. I found Fuding Ge's thesis to be pretty good.You can refer to that for your design.


amarnath
 

Could you tell me why the bandwidth should choose less than 1/10 of input frequency in more deepth ?or do you have some doc about this topic?
 

The PLL can be approximated as a continious time system only when we have no finite sampling effects, so to meet this requirement we need to keep the bandwidth less than 1/10 input frequency and another requirement is stability. You can refer to any text book on PLL's, for more info on the same


amarnath
 

First, it depends on what your PLL used for?
 

one correction to what amarnath has said. the loop bandwidth is 1/10th of reference frequency, not input frequency. reference frequency is the rate at which phase detector compares the phase of the input and feedback clocks.
 

Thank you for amarnath of explanation. but how can find Fuding Ge's thesis?
 

just search "fuding ge thesis pll" in google.


amarnath
 

Hi amarnath,

I didn't get the thesis from google. I f u have the link please give it.
 

option318 said:
Who can tell me, how to decide PLL LoopBandwidths?please tell me thanks.

it is up to your lock time which the system requires.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top