hi,there
I have drawn a nand2 gate.when i simulating it ,i found there are some burrs in the plot,do they cause some problem when i using them in a pipeline adc?how can i deburr these?
i'm using 90nm pdk
the problem arises only when they are deep enough to cross the threshold voltage of your gates.
You will always see in your logic signals due to switching of other logic gates (and it gets worse after pex).