How to debug the memory operation and content?

[Zeng Jie-jun]

Hi Friends.
I want to debug the memory operation and content. Could you please tell me how to dump the memory database in verilog and debug in Debussy?
Thanks in advance.

 

[funzero]

fsdb memory dump

if you use cadence ncsim .
you can try this
module tb;
initial $shm_open("waves");
initial $shm_probe("ACMS");
endmodule
which will dump all memory related signal to waveform database.

 

[aji_vlsi]

debussy memory dump

Hi Friends.
I want to debug the memory operation and content. Could you please tell me how to dump the memory database in verilog and debug in Debussy?
Thanks in advance.

From:
**broken link removed**

   $fsdbDumpvars(1, top, "+mda");

HTH
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

 

[mvkarthik]

fsdb dump memory

Hi,

All you need is the following statements

initial
begin
$fsdbvars(<hierarchy till the memory");
$fsdbDumpfile("<filename.fsdb">);
end

Hi Friends.
I want to debug the memory operation and content. Could you please tell me how to dump the memory database in verilog and debug in Debussy?
Thanks in advance.

Added after 1 minutes:

All you need is the following statements

initial
begin
$fsdbvars(<hierarchy till the memory");
$fsdbDumpfile("<filename.fsdb">);
end