How to deal with inout ports in VHDL?

[joinfaisal]

inout ports in VHDL

hello all..

Can any one tell me how to deal with inout port in vhdl.
I have a model like this

if(sel='1' and sel_not='0')then
Y <= X
else
Y <= '0';

now I want to do this bidirectionaly ie on same sel and sel_not signals...if we have input from Y then it should go to X.I declared X and Y inout and used another process like this

if(sel='1' and sel_not='0') then
X <= Y
else
X <='0';

now problem is this gives 'X' when simulating.I know the reason of this problem but I dont know proper way to do it.Can any one help...thnxxx in advance.

 

[Sparc]

inout ports in VHDL

Try using event attribute and include X, Y, sel, sel_not in the sensitive list. And in the if condition Put X'event or Y'event alongwith sel & sel_not.

 

[zape]

inout ports in VHDL

What are you trying to do? I think your condition "(sel='1' and sel_not='0')" equal in both "if" does not make sense, as it is written you can also say:

if (sel='1' and sel_not='0') then
x<=y;
y<=x;
else
x<='0';
y<='0';
end if;

What kind of logic is this?

 

[joinfaisal]

Re: inout ports in VHDL

sorry i put question in wrong way.....lets make it simple.... I want to input some data from x and output to y in a given way....

if(sel='1')then
y <= x;
else
y <= 'Z';

now I want that if I input my data from y and output from x then how to do it???? I declard x and y as inout port but simply doing this does not work for me...any body please help ugently....

waiting for the response....

 

[tkbits]

Re: inout ports in VHDL

An inout port signal models a single bidirectional pin on a chip. You cannot have signals going both ways simultaneously without interference.

If you are building synthesizable code for programmable logic, all outputs must be switchable to inactive ('Z') mode, and only one output can be active ('0' or '1') at any moment.

If you are only simulating, you can also experiment with weak logic, which gives you wire-OR'ing or wire-AND'ing depending on your point of view (active-high or active-low signals).

If you want signals to go both ways simultaneously, then you must use two separate port signals.

 

[vomit]

Re: inout ports in VHDL

Do you mean something simple like two back-to-back tristate buffers with either direction enabled:

y<=x when sel='1' else 'Z';
x<=y when sel='0' else 'Z';

?

This will pass the signal from one to another according to the sel direction.
At the other drivers of X and Y you will also need to stop driving the output otherwise you get X'es, of course.

If you mean that the Sel is like a transistor switch, with something like the following (non-VHDL) pseudocode:

if Sel='1' then
y <= x if x-side is driving
x <= y if y-side is driving
else
x<='Z';
y<='Z';
end if;

and there is no digital signal that can tell you which one is driving,
then you should have a look at the "switch" model in **broken link removed**, but remember that this is unsynthesizable (because there are no free gates to control in an FPGA, only tristate buffers).

Hope this helps.

 

[joinfaisal]

Re: inout ports in VHDL

thxx vomit and tkbits...

I dont want this to work simuntaneously in both direction but at a time in one direction.Now problem is as vomit mentioned that if signal goes from x to y then since y is inout port so this port will also be drived and result will be X.I dont know how to overcome this problem.Actualy I want to simulate the behavior of transmission gate in VHDL and I want transmission gate to work in both direction.
if someone has Idea to implement transmision gate or tristatebuffer which work in both directions that suggestions are welcome..

waiting for response.

 

[adap]

inout ports in VHDL

Hi joinfaisal,

Is it possible in your design to "break" X and Y into four signals instead of two? I mean to have X_in, Y_in as inputs and X_out and Y_out as outputs. This will simplify your problem and you don't need tri-state buffers.
Another way is to store the values of X and Y (when act as inputs) into temporal buffers temp_x and temp_y while reading and when sel = 1 to write these buffers to X and Y(when act as outputs) at the next clock edge. It's just a thought I haven't simulate it to see if it works.