bigdog
Junior Member level 2
Hello,
I compiled some gated clocks in my design, and when I do formal verification, the gated clock cells are in unmatch cell list, how can I tell Formality about the gated clock setting?
Regards,
I compiled some gated clocks in my design, and when I do formal verification, the gated clock cells are in unmatch cell list, how can I tell Formality about the gated clock setting?
Regards,