How to deal with gated clock in Synopsys Formality?

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bigdog

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Hello,

I compiled some gated clocks in my design, and when I do formal verification, the gated clock cells are in unmatch cell list, how can I tell Formality about the gated clock setting?

Regards,
 

if u have used DC to synthesize, dump out the svf file and read in to the formality which will take care of all the optimizations done in dc,
if not u can make a try , write the following commands to a file and read tat file in to formality with read_svf command
guide_environment \
{ { clock_gating latch_and } }
 

I used DC to compile the design and dumped the svf file too, after Formality reading the svf file, it wrote a file(svf.txt) that contants the statement "guide_environment \
{ { clock_gating latch_and } }", so I don't get the reason why Formality still doesn't pass the verification.
 

A clock gate is a new state point to Formality, you need to find the command to tell Formality to flatten the clock gate or make it a pass through cell.
 

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