ameed
Advanced Member level 4
hi all,
At the sub-nano technology nodes, the impact design-process interactions have on yield is becoming a huge factor and is very design-dependent. Expecting a designer to understand the nuances of the sub-nano process issues, and the process engineer to understand the design issues is very optimistic, but not realistic. Making sure that a design is less sensitive to litho and other layout-related yield loss issues is critical. One way to address this is to,
1. Give up the traditional independence and build better "inter-dependence" between the design and process teams
2. Jointly capture the required process intelligence and encapsulate them into design tools
3. Build the required automation into the tools to address the sub-nano issues right from the cell-library development stage of a flow
The advantage of addressing at the cell library level helps take care of these issues once, and not on a per design basis. Such a tool would enable layout designers with little or no process expertise to create DFM-optimized designs, by automatically addressing litho and other layout-related yield considerations like contact doubling and random defect sensitivity.
An automated tool that allows encapsulation of process intelligence to produce high-yielding library elements at sub-nano conditions is now available. Use of such DFM-optimized libraries would take away the pain for the downstream IC designer.
thanx.
At the sub-nano technology nodes, the impact design-process interactions have on yield is becoming a huge factor and is very design-dependent. Expecting a designer to understand the nuances of the sub-nano process issues, and the process engineer to understand the design issues is very optimistic, but not realistic. Making sure that a design is less sensitive to litho and other layout-related yield loss issues is critical. One way to address this is to,
1. Give up the traditional independence and build better "inter-dependence" between the design and process teams
2. Jointly capture the required process intelligence and encapsulate them into design tools
3. Build the required automation into the tools to address the sub-nano issues right from the cell-library development stage of a flow
The advantage of addressing at the cell library level helps take care of these issues once, and not on a per design basis. Such a tool would enable layout designers with little or no process expertise to create DFM-optimized designs, by automatically addressing litho and other layout-related yield considerations like contact doubling and random defect sensitivity.
An automated tool that allows encapsulation of process intelligence to produce high-yielding library elements at sub-nano conditions is now available. Use of such DFM-optimized libraries would take away the pain for the downstream IC designer.
thanx.