How to deal with clock latencies ?

[designer_ec]

Hi,

Pls anybody let me know that if we meet skew ,then we need to take cre of min insertion delay and max insertion delay.Pls let me know that what are the prections or what we consider before build clock tree for given constraints i.e for min insertion delay,max insertion delay and skew.

If any body having appliction note or any good meterial on clock tree synthesys,pls keep in this portal.

 

[MarcS]

Re: Latencies

The skew target for your CTS is easy - it is simply the clock uncertainty that was assumed during synthesis. It is typically given in the SDC file. If you want to know what clock uncertainty value you should choose, well that depends on your process technology and your clock speed. Obviously, a 200ps skew is not easily achievable at 130nm, but is probably OK at 40nm. Also, a 500ps skew is probably fine for a 5ns clock period but is unacceptable for a 1ns clock period. It all depends.

Clock latencies can get complicated, but here is the basic approach:

If you are building your chip bottom up like most people do, then you have no idea what the clock insertion delay should be, so just leave it out. Don't specify anything. The CTS tool will give you the best result it thinks it can get.

You only need to specify a target insertion delay if you are using a top-down approach where you define budgets and delay targets for each block in your floorplan at the top level. Then you pass these requirements down to the block level implementation CTS as a target.

If you are doing everything flat, then you don't care about insertion delay. You only care that it is not too big to avoid on-chip variation (OCV) problems increasing your skew.